<daveshah>
fpga is €16k, not actually bad given the ADCs and DACs alone wouldn't be super cheap
<rqou>
nah, don't have that kind of cash
<rqou>
if i were to do something of that scale i'd probably work on Project Lucoa (hey, blame pie_) targeting the arria in the g-sync monitors
<rqou>
btw azonenberg, any objections to that name? :P
<pie_>
here be dragons :O
* pie_
goes back to grinding haskell
<pie_>
tbh its more like coding python though because of imperative bindings...
<pie_>
except minus the mindfuck runtime errors
<pie_>
(ok now you have to figure out whats going wrong at compile time but its not too bad so far)
<rqou>
pie_: should try rust :P
<pie_>
yeah
<pie_>
i want to make a $$$ ymbol but for time
<pie_>
*symbol
<rqou>
⏰⏰⏰
<rqou>
also, azonenberg you should try rust
<rqou>
don't you like not having memory safety errors?
<pie_>
;3
<rqou>
and you get a nice powerful (but still reasonable) type system too
<pie_>
well until you shoot yourself in the foot with something weird but it cant be WORSE right? :p
<rqou>
it's designed to be practical, not for PL wankery
<rqou>
unlike haskell :P
<pie_>
except its better >> percent of the time
<pie_>
^ not @ haskell
<azonenberg>
rqou: lolol
<azonenberg>
thats an interesting feature :p
<azonenberg>
coolrunner has the same capability, but is not user writable
<azonenberg>
since there's no extra bytes available
<rqou>
um, ime sram programming doesn't actually work
<rqou>
oh wait, it can _also_ do the same thing as altera
<rqou>
and afaict that does actually work
<rqou>
but yeah, max v has a pretty neat 8192 bits available for user storage
<rqou>
azonenberg: btw, why do you hate Rust?
<azonenberg>
i hate rewriting existing projects in rust bc you dont like c++ :p
<azonenberg>
i need to learn rustm planning to play with it for antikernel
<rqou>
why don't you play with it sooner and convert to the dark side? :P
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<cr1901_modern>
>just $8995
<cr1901_modern>
Sure, I'll take twenty. Does Xilinx accept organs as payment?
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<awygle>
rqou: corner bit some kind of clock buffer enable?
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<rqou>
damn awygle you get up early
<rqou>
and no, those are in the middle
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<rqou>
wtf?
<rqou>
OFTC just banned me?
<sorear>
Probably just one channel?
<rqou>
"autokilled: Possible spambot."
<rqou>
great
<rqou>
IR time
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<sorear>
Killed isn’t a ban, can you rejoin?
<rqou>
huh, apparently i can now
<rqou>
i guess they were just doing weird maintenance?
<rqou>
earlier it was actually reporting "Banned"
<sorear>
Some weird shit was going on
<sorear>
#oftc blamed skiddies
<rqou>
ah ok
<rqou>
i was a little bit concerned because my server has some "fun" configurations that potentially could allow an attacker to get access to IRC
<rqou>
i run ZNC as a proxy for my crappy scripts to connect to IRC without having to deal with all of the difficulties of actually connecting to IRC like authenticating and reconnecting
<rqou>
this interface is bound to an internal IP but isn't authenticated
<rqou>
it's firewalled off so that only containers on the same server can use it
<rqou>
but one of the containers is the perpetual CVE magnet, jenkins
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<awygle>
rqou: I mean, 8am. Not that early.
<awygle>
I suggested clock buffers because some arches have like "quadrant" clock networks
<rqou>
yeah, those are also in the middle
<awygle>
but I guess that makes little sense on the chibiest fpga
<rqou>
it's per-column buffers in this case
<rqou>
it's actually quite obvious that they're there
<rqou>
"oh, i wonder what this one single row of bits controls? it's right in the middle, and every column has four bits, and there are 4 gclk wires"
<awygle>
Lol
<rqou>
although there is a trap
<rqou>
the first column of ios has enables too, but it doesn't have enough room for these bits
<rqou>
so these bits are shoved into the next column on the right
* awygle
has no food in the house
<awygle>
time for shopping
<rqou>
<insert that weird birbsite/weeb mcdonald's meme here>
<awygle>
...?
<rqou>
if you missed it, i'm not going to bother to dig through and try to find it
<awygle>
fair enough
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<rqou>
hmm, why does max v io have a dedicated open drain mode?
<rqou>
ah, it allows use of the fast path
<daveshah>
yeah, that is quite common in fpgas
<rqou>
huh, open-drain mode is configured in the "padring" bits
<rqou>
not the fabric bits
<daveshah>
Yeah, it's the same for the ecp5
<daveshah>
It seems that output enable for the ecp5, OTOH, is two bits on the fabric/IOLOGIC side