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<openfpga-github> [Glasgow] awygle commented on issue #35: I added these in commit 7c3203c126e7444981d5405d7d6fcd1db53bbbc5 https://github.com/whitequark/Glasgow/issues/35#issuecomment-399802748
<openfpga-github> [Glasgow] awygle commented on issue #51: Where'd you find 24 mA as the value? I'm looking at ... https://github.com/whitequark/Glasgow/issues/51#issuecomment-399803084
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<rqou> hmm, something is borked with the way global clock constraints work
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<rqou> yeah, partially constraining the clock path doesn't seem to work correctly
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<rqou> hmm, somehow there is a bit near the global clock muxes that _should_ be an invert bit, but i can't get quartus to generate it
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<balrog> qu1j0t3: replace it. That mouse has crappy middle click support
<balrog> And cleaning the scroll ball is a pain
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<rqou> so this is weird
<rqou> i am looking at the global clock muxes, and they take over some of the io muxes
<rqou> so this io cell only has 4 instead of 5, so that's fine i guess? except the die photo still shows 5 "things"
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<rqou> oh wat
<rqou> altera has an option to set the register power up level
<rqou> but it doesn't actually work or do anything
<rqou> 10/10 quality software
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<azonenberg> rqou: it DOES work
<azonenberg> But it doesn't do what you think it does
<rqou> how can it work if the bitstream shows zero bits changed?
<azonenberg> Were you using any registers?
<rqou> um, yes?
<azonenberg> or just setting the default
<azonenberg> Because in altera uarches, all registers power up to the "0" state
<rqou> i had one register and tried to set the default power-up state to "high"
<azonenberg> And setting them to initial "1" just adds an inverter before/after
<rqou> and nothing changed
<rqou> well, that didn't happen either
<azonenberg> in that case that eems to be a bug
<rqou> maybe it is, since i was instantiating a raw "atom"
<rqou> and i guess it couldn't figure out where it was supposed to push the inverts to or something
<rqou> there's an invert in the io cell, so it could have pushed it there
<rqou> and then inverted my lut
<azonenberg> yeah
<azonenberg> thats what would normally happen
<azonenberg> its possible it doesnt work when you do raw primitives or something
<rqou> so azonenberg, how's your house?
<rqou> did you finish all the stuff you needed to finish before the inspector shows up tomorrow?
<azonenberg> rqou: We just got out of the shower
<azonenberg> Which happened just after getting home
<rqou> is that a good thing or a bad thing?
<azonenberg> Well, we were at the house late
<azonenberg> :p
<azonenberg> We finished though
<azonenberg> The back deck light was a PAIN IN THE BUTT
<azonenberg> because of the way the geniuses sided the house
<azonenberg> they did something similar with the front door light but i had a different model of lamp which wasnt as big of a problem
<rqou> why does your house just seem to be disaster after disaster?
<azonenberg> Then the lights by the garage went fine, because that wall was nice shiny new siding with a hole i drilled specifically for those lights
<azonenberg> Because it's an old house built by a cheap builder to minimum standards
<azonenberg> That was lacking in basic maintenance over the last few years
<azonenberg> Retrofits in general are going to be more of a pain than new construction
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<rqou> hey azonenberg, want to help and try and understand howtf the lab-wide control signals work in this chip?
<rqou> the datasheet claims that there are 10 signals, but other sources claim that it's way more complicated than that
<rqou> datasheet claims 2x clk, 2x clk enable, 2x async clear, sync clear, async preset/load, sync load, and add/sub
<rqou> and datasheet mentions that clk and clk-enable are paired together such that there can only be two pairs
<rqou> but i have a different doc that mentions that also everything that uses async load has to use the same async clear, and anything that doesn't use async load has to use the same async clear
<rqou> and then anything that has sync load or clear used has to use the same sync load and sync clear as everything else in the lab
<rqou> so there's a whole bunch of other rules as you can see
<rqou> azonenberg: so, how to even begin tackling this problem?
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<azonenberg> rqou: oh the icing on the cake
<azonenberg> at 19:30 today
<azonenberg> With the caulk-and-seal inspection tomorrow morning, and three windows left to caulk
<azonenberg> My caulking gun died
<azonenberg> Not sure what failed but i was pulling the trigger and getting no resistance
<azonenberg> and nothing was coming out
<azonenberg> And the home depot closed at 20:00
<azonenberg> So that was a last-minute run :p
<rqou> wtf dude
<rqou> why is your equipment always broken?
<azonenberg> In this particular case, because i made the mistake of buying the basic model and not the heavy-duty model
<azonenberg> Thinking i wouldnt use it that much
<azonenberg> :p
<azonenberg> every time i buy a lower-end tool i pay for it later on
<azonenberg> oh and, another thing we had to do today
<rqou> i thought that was widely known?
<azonenberg> Yes but i didnt think there was even such a thing as a cheap or nice caulking gun
<azonenberg> :p
<azonenberg> anyway in order to caulk around the windows, we needed to have the wood pieces for the window well and sill done
<azonenberg> The office has that really deep well because of the new wall we framed and the gap for insulation
<azonenberg> All of the other windows we just used 1x3 or 1x4 pine boards
<azonenberg> But for that, we had to use plywood
<azonenberg> Since nobody makes 15" wide pine boards
<azonenberg> And cutting a lot of 3/4" plywood with a sawzall or hand saw, straight, is not a good idea :p
<azonenberg> So i ran out and bought a circular saw
<azonenberg> (another of those "what was i missing out on by not having this sooner" moments)
<rqou> I TOLD YOU TO DO THAT YOU KNOW :P
<azonenberg> lol well for small pieces like 2x4s a sawzall is fine
<azonenberg> But you really do not want to try to do a 4-foot-long straight cut with it
<azonenberg> aaanyway
<azonenberg> The clk/enable pairs seems like theres probably one bit
<azonenberg> for clka/ena or clkb/enb
<azonenberg> for the whole lab
<azonenberg> kinda like how xilinx has "control sets" where each slice has to use the same clk/en
<rqou> for now i've fuzzed out global clocks into the tile, without any enable
<rqou> just to see how that works
<rqou> whelp, problem
<rqou> afaict .rcf files cannot constrain which lab line gets used
<rqou> but i think i know which bit controls which clock line gets used
<rqou> but i have no idea how enables work
<rqou> oh btw, azonenberg: random guess: how likely is it that there is an inverter in the path from fabric->global routing?
<rqou> fabric->global routing lives in an io tile and uses a similar type of mux
<rqou> there is a bit that seems to correspond to an invert bit, but i can't get it to set
<azonenberg> very likely there's inversions everywhere
<azonenberg> seeing as nots are cheaper than buffers in cmos
<azonenberg> the coolrunner zia to pla, for example, inverts in the row drive buffer
<rqou> but this is a redundant invert
<rqou> seeing that all the drivers/sinks also have inverts
<rqou> i guess this might require hardware testing
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<rqou> aargh
<rqou> azonenberg: max v = muxes, muxes everywhere
<azonenberg> max mux? :p
<rqou> there's over 1700 muxes
<rqou> in a 240 lut part
<azonenberg> Sounds about right
<rqou> i guess i just never thought about just how much of an fpga is interconnect
<azonenberg> Lol
<azonenberg> there's a joke in the fpga world
<azonenberg> you can have all the luts you want for free
<azonenberg> But you have to pay for the wires
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* pie_ files that away
<rqou> hmm, why does it seem like the lab control muxes can only have 12 settings?
<rqou> not 18 like the lut input?
<daveshah> That is quite common I think
<rqou> it's also not the same shape as any other mux i've fuzzed so far
<daveshah> On the ECP5 the miscellaneous "M" signals have fewer settings than the LUT input muxes
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<rqou> heh, putting everything on a global track is a good way to make signals get out of the way
<pie_> mooom, youtube is putting weird shit in my suggestions again
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<rqou> alright, the bitstream is way more clear than the documentation when it comes to these control signals
<rqou> i have some idea what's happening, so more fuzz tomorrow
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<rqou> but basically there are muxes that choose a set of signals (LAB_CONTROL_MUX) and then some more muxes/control bits that actually control the function itself
<pie_> yay
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<qu1j0t3> balrog: Oh, believe me, I know
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<rqou> heh i see byuu rediscovering IPS
<rqou> what a shitty format
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<rqou> ok, i think i figured out wtf is going on with max v lab signals now after sleeping on it
<rqou> it's literally what's drawn in the datasheet
<rqou> all the words just serve to confuse the issue
<rqou> the only thing is that you have to squint at the diagram because it's drawn poorly
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<awygle> Lol
<awygle> Should have listened to Gloria Estefan
<awygle> Words get in the way
<daveshah> There is a table in the ice40 datasheet describing what globals can drive what signal types, and its wrong but the adjacent text is correct
<daveshah> So it does go both ways
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