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<awygle> lol the DIY post reminds me of that dumb thing we almost did with the 2x2s before we realized it was dumb.
<pie__> lol tfw not being dumb
* pie__ closes imgur
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<prpplague> pie__: hehe i was waiting for someone to post that
* prpplague has got to clean his office tonight
<pie__> ive been sayin that about my room for months...
<prpplague> i usually clean on sunday nights
<prpplague> but i've been swamped and haven't cleaned in like 3 weeks
<prpplague> the office now resembles downtown mogadishu
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<prpplague> i know putting my 555 chips in the storage box for 7400 series is wrong... but it feels so right...
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* prpplague pours a beer and starts cleaning
<prpplague> tinyfpga: could really use a pdf schematic posted for the tinyfpga project board...
<prpplague> tinyfpga: minor complaint, hehe
<openfpga-github> [Glasgow] whitequark pushed 1 new commit to master: https://github.com/whitequark/Glasgow/commit/a0ef64df566777164451c618453c92ab67e5eced
<openfpga-github> Glasgow/master a0ef64d whitequark: applet.i2c.eeprom: improve resiliency in face of bus errors.
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<whitequark> so I got pretty paranoid after adding an 1.8V component to one of my designs
<openfpga-github> [Glasgow] whitequark pushed 1 new commit to master: https://github.com/whitequark/Glasgow/commit/f8afe868a4509e2429de7b54b933f409f7514e57
<openfpga-github> Glasgow/master f8afe86 whitequark: Allow programming a non-volatile voltage limit, as a safety feature....
<azonenberg> whitequark: i love design features like that
<azonenberg> safety limits you can configure for a given deployment that keep it from doing something stupid
<azonenberg> my R&S PSUs have that
<azonenberg> you can set a limit for voltage or current and the interactive adjustment dial refuses to go beyond that
<whitequark> it even protects you against DAC/LDO failure, assuming you're smart enough to connect Vsense to the target
<whitequark> well, and assuming it is still able to disable the DAC/LDO
<whitequark> so it's *two* layers of safety
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<azonenberg> yeah awesome
<azonenberg> my PDU had similar stuff, it had UV/OV lockout that would hard shutdown all the outputs
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<openfpga-github> [Glasgow] whitequark pushed 3 new commits to master: https://github.com/whitequark/Glasgow/compare/f8afe868a450...5665ad658066
<openfpga-github> Glasgow/master 02f390b whitequark: gateware.i2c_regs: forward any add_* args to Signal()....
<openfpga-github> Glasgow/master 5665ad6 whitequark: target.access: allow making pin and pin set arguments required.
<openfpga-github> Glasgow/master 30726ca whitequark: applet.i2c_master: use reliable out-of-band reset instead of in-band.
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<cr1901_modern> azonenberg: Any possibility you could take a look in the next few days? https://github.com/azonenberg/pcb-checklist/pull/1
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<azonenberg_work> whitequark: interesting re coolrunner
<azonenberg_work> "Xilinx has extended the life span commitment for these devices, now offering supply beyond 2024 for customers starting new designs."
<azonenberg_work> so not exactly a dead chip
<azonenberg_work> i wonder who's still using them?
<daveshah> Random control and sequencing in telecoms etc I would imagine
<azonenberg_work> i know i saw one inside a FEI SEM/FIB circa 2014
<azonenberg_work> (and it was a new design too)
<azonenberg_work> i think i've seen one or two in client hardware over the years too
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<mithro> This is pretty cool -> https://hackaday.io/project/158981-kubik-m0 :-P
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<pie_> some studentish rocket launch thing
<awygle> oh cool
<pie_> idk the context, xpost from some other chan
<awygle> well i'll come back in ~2.5 hours for the launch lol
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<pie_> awygle, almost forgot, theyre launching soon
<pie_> says heating tank to 60 bar, theyre at 40
<pie_> man must be a long day there
<openfpga-bot> [jtaghal-apps] azonenberg pushed 1 new commit to master: https://git.io/fN0of
<openfpga-bot> jtaghal-apps/master 48040a4 Andrew Zonenberg: Added lots of new commands
<jn__> pie_: it's on the big screen now
<openfpga-bot> [jtaghal] azonenberg pushed 1 new commit to master: https://git.io/fN0om
<openfpga-bot> jtaghal/master 7669f26 Andrew Zonenberg: Lots of refactoring of ARM debug stuff, moving it to base class
<jn__> (@ cccac)
<pie_> jn__,meh you have a hackerspace :P
<openfpga-bot> [jtaghal-cmake] azonenberg pushed 1 new commit to master: https://git.io/fN0oO
<openfpga-bot> jtaghal-cmake/master f49ce18 Andrew Zonenberg: Updated to latest submodules
<pie_> yeah i figured :D
<pie_> ok nw its 41, so i guess this will take a while
<awygle> lamps to pressurize the tank feels pretty inefficient and also slow
<awygle> (but very safe which is probably a good thing)
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<pie_> awygle, yeah i was scratching my head about that but idk anything about rockets so
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