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<Zorix> anime nerds...
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<pie__> dumb question, is there a commonly named function that always rounds up?
<rqou> ceil
<pie__> ohh right i _totally_ forgot floor and ceil are a thing
<pie__> heh :I
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<pie__> rqou, ugh, finally made some progress on what ive been working on so i just have to share https://i.imgur.com/nmy1vhy.png
<pie__> now you can actually navigate, sort of. \o/
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<mithro> daveshah: I'm trying to understand the ice40 timing data - what I don't understand is how which of the Span4Mux_hX are used when? So far the best I have found is https://github.com/cliffordwolf/icestorm/blob/master/icetime/icetime.cc#L1952-L2025 ?
<daveshah> mithro: yeah, as I understand it the number is basically a length
<mithro> oh?
<daveshah> in reality I think icecube has a few heuristics based on loading that icetime doesn't replicate
<daveshah> hence the max_span_hack, if you need a strict lower bound
<daveshah> but icetime is accurate enough without it
<daveshah> I've never seen it off by more than 1MHz
<daveshah> you're probably better off asking clifford for the details though
<mithro> daveshah: I don't quite understand how/what the create_cells function is doing
<daveshah> mithro: basically it is converting interconnect to a series of "mux" cells
<daveshah> Because that is how routing delays in the ice40 are represented
<mithro> But I don't quite understand how that maps to the Span4Mux https://github.com/cliffordwolf/icestorm/blob/master/icetime/icetime.cc#L1987-L1991
<daveshah> What timing netlist does that produce?
<daveshah> That's not a timing netlist
<daveshah> I mean the Verilog netlist output
<mithro> I'm trying to figure out what part of the verilog file that maps too
<daveshah> From memory, every routing connection onto a span4, including from another span4, creates one
<daveshah> It would probably be best to start with something very small first
<daveshah> So it looks like there is a span4 connection of length 4 mapped to a Span4Mux_h4
<daveshah> Then a vertical one of length three goes to a Span4Mux_v3
<mithro> Where does the length come from? Isn't a sp4 always 4 length?
<daveshah> But not all that four may be used
<daveshah> E.g. you might route off after only going up 3 tiles
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<mithro> Okay - so Span4mux_h0 - means you only went 1 tile? Span4mux_h4 means you went the full 5 tiles? (horizontally?)
<daveshah> Yeah, I think so
<daveshah> Might be worth pinging clifford to check
<mithro> There also seem to be Span4Mux_s0_h
<daveshah> mithro: that is the Lattice cell name I think
<daveshah> I don't think icetime uses those, I think the fuzzer converts them to _h0
<mithro> Versus the icestorm names?
<daveshah> mithro: this would convert _s0_h to h0 for example
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<mithro> // Timing estimate: 1.27 ns (786.63 MHz)
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<G33KatWork> does anybody here have experience with debugging a core on a zynqmp with openocd?
<G33KatWork> I thought I found a target config for openocd recently but I can't find it anymore
<G33KatWork> and it's not in the official openocd repo
<G33KatWork> ha. nevermind. I just looked in the wrong place. it is there: https://github.com/ntfreak/openocd/blob/master/tcl/target/xilinx_ultrascale.cfg
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<mithro> Does this make sense?
<mithro> daveshah: I'm guessing you are not around?