<mithro>
But it might be better to use an actual PDF parsing tool
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<kc8apf>
Easier to call C/Rust from Python. Keep the outer shell Python and replace the internals
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<kc8apf>
Rust methods with #[no_mangle] and built as a dylib turn into plain C methods
<kc8apf>
Err C symbols
<awygle>
kc8apf: yes, but that means you either have to replace everything up front, or stick with python for the rest of the program, or call python from whatever you choose to use next anyway
<rqou>
azonenberg, awygle: do you use solder paste for BGAs or flux only?
<awygle>
flux only usually
<rqou>
if i use paste, do I need to very very carefully align the bga?
<awygle>
it'll still self-center. just be careful not to use too much.
<rqou>
will smearing the solder paste cause everything to short?
<awygle>
i mean smearing is rarely good
<rqou>
i find that that tends to happen when placing small passives at least
<reportingsjr>
holy moly, the new version of kicad is finally out
<reportingsjr>
my fixes from 2 years ago are now released to the wild, woohoo
<prpplague>
reportingsjr: yea, v5 has made a lot of improvements
<prpplague>
reportingsjr: it's good to see so many companies throwing their weight behind kicad
<prpplague>
reportingsjr: the next 2 to 3 years for kicad are going to be critical to it's long term success
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<awygle>
whitequark: ltspice is the worst, but i have something here, more or less. assuming a 50 ohm transmission line, terminating in a high impedanace, a 37 Ohm resistor produces critical damping with a rise time of 1.6ns and negligible overshoot. conversely, a rise time of 20ns (50 MHz) to 2.9 V can be achieved with a 660 Ohm resistor
<awygle>
50 Ohm transmission line is a bad model for this case though, so now i'm thinking about ribbon cable impedance
<openfpga-github>
Glasgow/master d2227e3 whitequark: applet.uart: log actual port voltage.
<openfpga-github>
Glasgow/master 77f0526 whitequark: applet.uart: restore fcntl flags on stdin as well....
<awygle>
looks like a decent answer is 100 ohms, in which case 87 Ohms produces approximately critical damping and a rise time of 2.7 ns or thereabouts
<awygle>
whitequark: this is for the DUT side, where i feel like our primary concern is signal integrity, so something like 82 or 91 appeals to me
<awygle>
there's never going to be a right answer though because we don't control the cable
<awygle>
let alone the DUT
<whitequark>
right
<whitequark>
so we should go with ~37 ohms between iCE40 and FXMA, and ~100 ohms between FXMA and DUT?
<awygle>
that'd be pretty optimum from a signal integrity standpoint yeah
<awygle>
the only wrinkle is if the glitching you saw is our PDN collapsing rather than ringing/EMI
<awygle>
then we might want to go higher
<awygle>
but i doubt that
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<whitequark>
yeah I doubt it too
<whitequark>
there's way too many capacitors
<rqou>
azonenberg: soooo, BGAs 100%, QFPs 0%
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<awygle>
rqou: but what about QFNs?
<awygle>
whitequark: okay do you want to pick the MPNs or should I?
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<whitequark>
awgo ahead
<awygle>
lol
<awygle>
I assume that's a missed tab but still, lol
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<whitequark>
lol
<whitequark>
no itwas uh
<whitequark>
some way irssi tmux and mosh interacted
<azonenberg>
rqou: i use paste for my bgas
<azonenberg>
i have used flux with good results but most of the time i have paste on all of the other components
<azonenberg>
adding a process step seems stupid
<azonenberg>
The incomplete solder coverage could be a combination of oxides on the paste, old flux, insufficient time above liquidus, insufficient peak temperature
<azonenberg>
But it mostly screams oxidation to me
<azonenberg>
so really old paste?
<azonenberg>
It might be too fast heating too
<azonenberg>
if you are IR reflowing you might be melting the paste before the board hits the melting point of the solder
<azonenberg>
so as it sprreads out it cools
<azonenberg>
a slower ramp could help with that
<azonenberg>
my convection oven is very even so PCB and paste temperatrues are always almost equal
<azonenberg>
rqou: re yield, that is pretty typical with my experience
<azonenberg>
i mean my qfp yield isnt that bad
<azonenberg>
but my BGA yield is normally >> the QFP yield
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<rqou>
with the annoying shorts that took ages to try and clear
<rqou>
somehow it seems i'm printing too much paste for the QFPs
<rqou>
azonenberg: feature request
<rqou>
azonenberg: can jtaghal gain boundary-scan short-circuit checking?
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<azonenberg>
Yeah bgas are quite forgiving
<azonenberg>
surprisingly so
<azonenberg>
you see why i hate qfp now and use bga every chance i get? :p
<rqou>
yeah QFPs kinda suck
<azonenberg>
re the shorts, smaller paste pads may help
<azonenberg>
But clearing a short with sac305 should be almost instant if you have things set up right
<azonenberg>
Regarding boundary scan, file a ticket but i make no promises i'll get to it quickly
<azonenberg>
i wanted to do some playing with bscan too though
<rqou>
i was finding that _most_ of the short would clear
<azonenberg>
So might happen
<rqou>
leaving a tiny bit only visible under the microscope still shorting the pins
<azonenberg>
One of the problems is that you need to either hard code intelligence about how the bscan register is set up (like i do with programming algorithms)
<azonenberg>
Or have a BSDL parser
<azonenberg>
Which means a VHDL parser
<rqou>
which i have :P
<rqou>
not complete enough for vhdl but maybe good enough to read most BSDLs?
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<azonenberg>
in c++? :p
<rqou>
kinda
<rqou>
in flex/bison
<rqou>
also, the ft232h enumerates
<rqou>
so at least there's that
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<mithro>
rohitksingh: Thanks!
<mithro>
Morning everyone!
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<rqou>
azonenberg: i suddenly realized why my QFPs had too much paste
<rqou>
i probably didn't scrape it close enough to the stencil
<rqou>
previously they were only calling numbers associated with Chinese-sounding names
<prpplague>
rqou: i meant to comment, you need to make sure you have an extremely flat surface to do your stencil, my preferred base is a MFD based clip boards
<prpplague>
rqou: inexpensive and usually very flat
<rqou>
I'm using a scrap piece of acrylic
<prpplague>
rqou: ahh
<prpplague>
rqou: good deal
<rqou>
yeah, by-weight scrap acrylic from tap plastics is pretty neat
<prpplague>
rqou: and of course if you put too much pressure on the paste when scraping it, it will squeeze under the stencil
<azonenberg_work>
i use scrap PCBs
<azonenberg_work>
and that, to me, means that your stencil isnt flat against the pcb
<azonenberg_work>
or the stencil moved
<azonenberg_work>
i've only had squeeze-out issues with insufficient pressure when the stencil wasnt in firm contact
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<prpplague>
azonenberg_work: yea, it depends on the size of the pcb of course, because you get some flexing in the middle the bigger it is
<prpplague>
azonenberg_work: making your own little stencil board can be problematic at times
<azonenberg_work>
You do still need a good sized margin aroudn them to work it seems
<prpplague>
azonenberg_work: indeed
<azonenberg_work>
And it wont work on large boards (more than 200x160 mm) but still...
<azonenberg_work>
That is a *very* attractive option
<prpplague>
azonenberg_work: i have a framed stencil press for the larger boards
<azonenberg_work>
i've used one at a professional shop
<azonenberg_work>
But with that price it's plausible to use in my home lab
<prpplague>
azonenberg_work: i jsut like the frameless for small boards and smaller qty, i.e. less 100 pieces
<azonenberg_work>
I am definitely going to get one after the new lab is set up
<awygle>
oh yeah that's pretty cool
<azonenberg_work>
gotta try to find a US dealer for it though
<awygle>
and not unreasonably priced
<azonenberg_work>
overseas shipping for that might be a bit $$$
<awygle>
tru
<rqou>
wat almost 1k Euros?
<rqou>
way too expensive for me
<prpplague>
azonenberg_work: i searched for a long time to find a US dealer
<prpplague>
azonenberg_work: i was unsuccessful
<prpplague>
azonenberg_work: olimex was good about shipping and such
<prpplague>
azonenberg_work: reliable source
<prpplague>
azonenberg_work: iirc it was about $125 shipping
<azonenberg_work>
rqou: for somebody like me, though, totally worth it
<rqou>
i mean, my super janky stenciling seems to kinda work
<rqou>
at least the BGAs worked
<rqou>
I'd rather buy a cnc mill and then make a stencil jig :P
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<rqou>
gruetzkopf what's wrong with your connectivity?
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<qu1j0t3>
rqou: yeah i'm curious about that too, also attaching a laser as a tool on a cnc
<rqou>
already have a laser that isn't set up properly
<awygle>
don't put the tube in backwards
<rqou>
don't look at laser beam with remaining eye
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<openfpga-bot>
[jtaghal] azonenberg pushed 2 new commits to master: https://git.io/fN89h
<openfpga-bot>
jtaghal/master 8f4858c Andrew Zonenberg: Refactoring: JtagDevice now takes IR length as a constructor argument
<openfpga-bot>
jtaghal/master deaaaff Andrew Zonenberg: Initial i.mx support
<awygle>
at my former employer we burned an intern with an unkeyed laser tube
<awygle>
not badly, fortunately
<rqou>
O_o
<rqou>
i bet legal was less than amused
<rqou>
interestingly, the lab my sister works in at $OTHER_FANCY_SCHOOL also has a janky Chinese K40 laser
<rqou>
when i warned her about it, she said "oh yeah, one of the grad students actually added a safety interlock"
<awygle>
yeah idk what all happened on that side
<awygle>
i bet she just signed whatever they gave her :/
<awygle>
that cutter was a menace, the instructions for grounding said "insert wire into underground" and showed a picture of a bare copper wire just lying in a planter, not even buried
<qu1j0t3>
...
<rqou>
i mean, K40s have an analog current sensor on the HV high side
<rqou>
so hope you don't get any unexpected short circuits
<prpplague>
<azonenberg_work> rqou: for somebody like me, though, totally worth it
<prpplague>
azonenberg_work: you do assembly on a regular basis?
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<azonenberg_work>
prpplague: regular enough that i want a better tool for it, yes
<prpplague>
azonenberg_work: ahh
* prpplague
makes a mental note
<prpplague>
azonenberg_work: i always like to keep a list of people doing this type of work as to trade tips and tricks with
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* awygle
waves
<azonenberg_work>
prpplague: my current "big project" on hold until i finish this move and get my new lab set up
<azonenberg_work>
is a 24+4 port 1G/10G Ethernet switch
<azonenberg_work>
1U fully managed
<azonenberg_work>
i have the line card PCB almost finished but not fabbed, still have to do the brain and backplane
<prpplague>
azonenberg_work: nice! something you plan to sell?
<prpplague>
azonenberg_work: or just some hobby thing?
<azonenberg_work>
prpplague: For the moment, just for fun
<azonenberg_work>
i dont want to deal with the hassle of making it a business
<azonenberg_work>
Which is why i work in consulting, i let other people worry about how to take the idea and make it a product
<azonenberg_work>
and sell it and do regulatory approvals and all that stuff
<azonenberg_work>
I live firmly in the R&D domain where i dont have to touch any of that
<prpplague>
azonenberg_work: hehe, i hear you loud and clear, hehe, i am the same way
<azonenberg_work>
rqou: btw sheetrock finally got here
<azonenberg_work>
but i'm at work and cant do anything with it quite yet
<azonenberg_work>
And we still have a few more tidbits of insulation to hang above the stairs
<prpplague>
ugh sheetrock
<rqou>
woohoo
<prpplague>
sheetrock work is some _serious_ work
<rqou>
only took ridiculously long as usual
<azonenberg_work>
prpplague: well i just rewired the whole house
<azonenberg_work>
And redid all the insulation
<azonenberg_work>
this is among the easier pieces of work we're doing :p
<azonenberg_work>
But when all is said and done i'll have fiber and cat5 to every room of the house
<prpplague>
azonenberg_work: hehe, yea, i just find sheetrock work very taxing
<openfpga-bot>
[jtaghal] azonenberg pushed 1 new commit to master: https://git.io/fN8FJ
<openfpga-bot>
jtaghal/master c012b8e Andrew Zonenberg: Refactoring: Added JtagDevice::PostInitProbes()
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<openfpga-bot>
[jtaghal] azonenberg pushed 1 new commit to master: https://git.io/fN8N2
<openfpga-bot>
jtaghal/master 81be883 Andrew Zonenberg: Fixed wrongly overwritten variable in constructor
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<openfpga-bot>
[jtaghal] azonenberg pushed 2 new commits to master: https://git.io/fN8NP
<openfpga-bot>
jtaghal/master 926c810 Andrew Zonenberg: Fixed copyright date
<openfpga-bot>
jtaghal/master 02b18d1 Andrew Zonenberg: Added JtagDummy for taking up space in scan chains when we have unknown devices
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<awygle>
azonenberg_work: did you price movers for your upcoming relocation at all?
<azonenberg_work>
awygle: i have a friend with a 20-foot box truck and a friend of his
<azonenberg_work>
for an hourly rate
<azonenberg_work>
:p
<awygle>
lol
<prpplague>
i hate moving, i usually just sell 90% of my stuff and start fresh, hehe
<azonenberg_work>
prpplague: most of the stuff i'm moving is expensive lab / test equipment :p
<prpplague>
azonenberg_work: yea that is the 10% hehe
<azonenberg_work>
i do have some stuff i'm cleaning out / getting rid of though
<azonenberg_work>
for example, an old sgi origin 2000 rack
<azonenberg_work>
(rack only, no compute nodes)
<azonenberg_work>
But monochroma already claimed that
<rqou>
wait you had _another_ spare server rack?!
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<azonenberg_work>
rqou: i at one point owned four racks
<azonenberg_work>
The one you grabbed
<azonenberg_work>
sorry, five
<azonenberg_work>
the 2-post aluminum rack in the office corner that i have the switch and patch panel on
<azonenberg_work>
The 2-post rack on my desk that i have all of the power supplies and test equipment on
<azonenberg_work>
The new black 4-poster with square cage nuts that is my new primary rack
<azonenberg_work>
and then the SGI rack in the garage
<azonenberg_work>
that one isn't very deep and doesn't have cage nut support so it's not suitable for modern gear on rails
<azonenberg_work>
Which is why i'm giving it away, it's a piece of history and i want to see it preserved
<azonenberg_work>
i just have nowhere to put it
<rqou>
isn't your new house "somewhere to put it?" :P
<rqou>
meanwhile i just picked up a giant pile of junk from our office move
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<awygle>
i need a rack. i'm too cheap tho.
<awygle>
actually i have a two-post desk rack now but i need rack mount kits
<openfpga-bot>
[jtaghal] azonenberg pushed 1 new commit to master: https://git.io/fN4Jk
<openfpga-bot>
jtaghal/master be63e01 Andrew Zonenberg: Initial work on heuristics for attaching i.mx SDMA to SoC TAP
<openfpga-bot>
[jtaghal-cmake] azonenberg pushed 1 new commit to master: https://git.io/fN4Jq
<openfpga-bot>
jtaghal-cmake/master bbfbfba Andrew Zonenberg: Updated to latest jtaghal
<openfpga-bot>
[jtaghal] azonenberg pushed 1 new commit to master: https://git.io/fN4Jd
<openfpga-bot>
jtaghal/master 2ed8d77 Andrew Zonenberg: Moved some debug messages to trace severity
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<azonenberg_work>
rqou: no i am buying a new 4-post rack for the new lab
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<rqou>
heh, helldesk at $WORK was unimpressed with my request of "i stole an ancient crappy monitor from an empty desk during our office move, can i get a dongle for it" :P :P
<azonenberg_work>
cyrozap: yeah i'm looking for a C++ library
<azonenberg_work>
I may have to write one
<cyrozap>
Right, but if you wanted to have something workin _now_ you could use my code to dump the AST of the BSDL to JSON, then parse the JSON to do the short-checking :)
<rqou>
huh, BSDL is a really small subset of VHDL
<cyrozap>
And I'll probably write a Rust BSDL parser... eventually...
<rqou>
doesn't have the insanity around `name`
<cyrozap>
rqou: Yeah, BSDL is actually fairly simple.
<cyrozap>
Well, simple-ish.
<azonenberg_work>
rqou: yeah i am seriously considering making a quick-and-dirty implementation that just strips out comments
<azonenberg_work>
then string-searches for a couple of keywords
<azonenberg_work>
and pulls out the pin naming database
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