<mithro>
daveshah: I'm trying to split the timing stuff into lut / ff parts
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<mithro>
daveshah: I think I'm missing something here... the Span12Mux_h0 has a larger delay (112.745) than the Span12Mux_h1 (107.108)?
<daveshah>
mithro: I don't understand what the lcout->clk path is? is it not clk->lcout?
<daveshah>
ad Span12Mux_h0, it could be how the switchboxes are positioned or something, neither are likely to be used often but I'll ping clifford
<mithro>
clk-lout
<mithro>
Opps
<daveshah>
lout->clk seems fine
<mithro>
I mean clk-ltout verse clk-lcout
<daveshah>
but the lcout path either starts from the inputs, if the FF is bypassed, or the clock if nit
<daveshah>
mithro: there is no clock to ltout path
<daveshah>
there is a ltout to clock "path" - setup/hold constraints if you like
<mithro>
daveshah: If I understand correctly, ltout is the delay from input->output of the LogicCell40 when the ff isn't used, while lcout is the delay from input->output of the LogicCell40 when the ff is used -- thus the difference between ltout / lcout must be the delay introduced by using the ff?
<daveshah>
mithro: nope
<daveshah>
lcout is always the normal logic cell output
<daveshah>
lout is the LutCascade output
<daveshah>
afaik
<daveshah>
the combinational input->lcout paths are used if the FF is disabled, input->clock setup/hold plus clock->lcout ones if it is enabled
<mithro>
You mean ltout ?
<daveshah>
yeah
<daveshah>
lout is it's name in icebox
<mithro>
Oh - lcout is used to cascade to the next lut inside a tile?
<daveshah>
other way round!
<daveshah>
lcout is the normal output ie luffk/out
<daveshah>
lout is the LUT cascade output ie lutffk/lout
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<mithro>
But really ltout can be thought of as *just* the lut output delay as the lut output is driven to the input of the next lut in the cascade and the FF select input mux?
<daveshah>
mithro: Yes, although it may consider that that output uses different internal routing too
<mithro>
btw - Is it normal for device to have different delays for high to low verse low to high transitions? And if so - what do you do with that information?
<daveshah>
mithro: yes, that is standard for all silicon (CMOS anyway)
<daveshah>
ASIC tools certainly make heavy use of it
<daveshah>
you'd really need a proper STA tool with SAT capabilities to work it out
<mithro>
But you don't really know what the signal going through the circuit is?
<daveshah>
e.g. if you have two inverters in series, you can work out that some combinations of transitions are impossible
<mithro>
daveshah: So, "safe" at the moment would just be to take the biggest value?
<daveshah>
mithro: yes
<daveshah>
I'm not even sure if Lattice's tools really use the values separately
<daveshah>
a timing simulator would use them though
<mithro>
Yeah
<daveshah>
hence why Lattice's tools dump them in the sf
<daveshah>
*sdf
<mithro>
I'm still confused at when to use the Span12_h7 etc muxes...
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<azonenberg>
mithro: I charaterize both rising and falling edges for greenpak
<azonenberg>
but my STA tool currently is pessimistic and uses max(rising, falling) at every hop
<daveshah>
mithro: Using a h7 mux for interconnect crossing 7 tiles should be fine
<daveshah>
the reality is even icetime doesn't get it 100%, but it's more than accurate enough for signoff let alone a PnR estimate
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<sorear>
naive question: how part specific are timing analysis tools? it seems like it should be possible to have a tool that spits out netlists with timing annotations, and then run all of the SATy bits in a generic way? it also seems like parts of verilog are designed specifically to express such annotated netlists?
<daveshah>
yeah, there are generic timing analysis tools but most are more ASIC specific
<daveshah>
OpenTimer being by far the best, as far as I know
<azonenberg>
i havent had time to look at any for greenpak as my focus was on gathering the timing data experimentally
<azonenberg>
because the chip vendor says the part can run from 1.8 to 5V
<azonenberg>
but doesnt provide multi-corner timing data, only typical at 1.8, 3.3, and 5
<daveshah>
azonenberg: the problem with that is presumably the unknown factor of process variation?
<daveshah>
I imagine you'd need samples of chips from a range of date codes to get decent numbers
<azonenberg>
Yes, i actually got them to send me SLG46620's from three production lots for this exact purpose
<azonenberg>
then got too busy with the move to finish the analysis
<azonenberg>
I have a characterization board that's supposed to mount to a Peltier plate
<azonenberg>
with a thermal sensor so i can control Tj to better than +/- 1C
<azonenberg>
then the board has a DAC to control VCC already
<mithro>
The question is about the Sp4_mux_?? one -- that would be a sp4_mux_?1
<daveshah>
mithro: a h1 I think
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<mithro>
daveshah: It looks like the CascadeMux is internal to the tile and does the LUT cascade?
<daveshah>
mithro: indeed
<mithro>
daveshah: Started adding the global muxes I think?
<mithro>
Lunch time for me
<daveshah>
mithro: looks good
<daveshah>
CLK can also be driven by INV
<mithro>
daveshah: It looks like CEMux can be driven by LocalMux in some way?
<daveshah>
mithro: yeah, if CE is driven by a local track
<daveshah>
mithro: the ??? on the IO could be Odrv4, Odrv12 or LocalMux
<mithro>
daveshah: Is GlbMux on the driver of the global track, or on the outputs? (does it make a difference?)
<daveshah>
have a look at the "Sinks driven" for the cells in the timing html output
<mithro>
daveshah: The ??? is suppose to end up driving the global track
<daveshah>
so i think that is a PRE_IO_GBUF and a gio2CtrlBuf
<daveshah>
i think there is just one GlobalMux per global
<mithro>
Dunno how clifford made sense of this without shitty diagrams like this :-P
<mithro>
Anyway, really lunch time now
<daveshah>
the sinks/sources driven/driving in the html list things quite well
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<rqou>
complaint: wtf is wrong with J2EE people
<qu1j0t3>
specifics?
<rqou>
everything is just overcomplicated
<rqou>
with fancy names to obfuscate everything
<jn__>
it's the EnterprisePaycheckFactory
<prpplague>
hehe
<rqou>
e.g. why is everything a "bean?"
<rqou>
that doesn't seem to actually mean anything
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<rqou>
e.g. $THING I'm currently looking at has at least 10 classes that basically contain no code
<rqou>
at best some one-line getters and setters
<sorear>
rqou: it's a part of a plant relevant to production of java (drink)
<sorear>
it's named after a pun.
<rqou>
i mean, i know that
<rqou>
but why use a stupid pun that doesn't convey any useful information?
<sorear>
well AFAIR it was mostly competing with ActiveX. go ahead, tell me that's a better name
<prpplague>
rqou: i am sure there is some beanaficial reason....
<sorear>
back when everyone thought that the future of programming was dragging and dropping modular components into VB6, and Sun wanted to get a piece of the future too
<rqou>
I'm curious now how often people actually write Java code rather than writing tools to autogenerate more Java code
* sorear
used 1.1 and 1.2 when they were new, and hasn't really touched it since then
<rqou>
i don't think I've ever seen one of these so-called modular components actually be properly modular
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<qu1j0t3>
turns out OOP doesn't REALLY foster code reuse.
<pie___>
qu1j0t3, well i mean...maybe theres MORE code so you reuse more?
<pie___>
xD
<pie___>
thats not exactlywhat i want to say but maybe you get what i mean
* qu1j0t3
reuses pie___ 's code
<pie___>
no dont do that yet thats not a good idea yet