<q3k>
azonenberg_work: ... yet another case of cultural differences appearing when you don't expect them to
<q3k>
azonenberg_work: would never uncompress 'mag' to 'magazine' unless given a very strong context
<q3k>
... and I'm happy with that.
<azonenberg_work>
q3k: you dont even have to be a gun person, magazine pouches are readily available, inexpensive, and fit various kinds of load-bearing gear, velcro, etc
<azonenberg_work>
i have an M16 mag pouch on my search-and-rescue gear for holding my GPS
<mithro>
rqou: It could just be normal cost modeling type of thing -- when something gets really long it's cost gets really expensive?
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<buhman>
I just learned about arachne-pnr and icestorm, and they at least project (more supported targets, etc..) the appearance that they are more mature than openfpga. Is openfpga fundamentally better in some way?
<rqou>
esden: apparently there's also a T3 test set
<rqou>
esden: i don't really know what you're trying to do, but if you write a "proposal" i can definitely let you borrow these
<azonenberg>
buhman: this channel is a general open fpga projects channel
<azonenberg>
the azonenberg/openfpga repo is specifically for greenpak right now but i planned to put other stuff in there too
<azonenberg>
a lot of the icestorm, prjxray, symbiflow, etc team hangs out here
<rqou>
azonenberg: um? xc2par?
<azonenberg>
rqou: oops yeah
<azonenberg>
lol
<azonenberg>
(can you tell i'm overworked?)
<azonenberg>
buhman: and my tools and theirs are for different chips
<azonenberg>
so, depends on what silicon you want to use :p
<azonenberg>
we all collaborate though
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<buhman>
is targeting different chips the only unique goal between each project?
<azonenberg>
so, xbpar was originally meant to be a generic CPLD place-and-route that could be used for multiple chips
<azonenberg>
I was going to do one for greenpak, one for coolrunner, maybe one for some older altera parts, etc
<azonenberg>
but rqou had to go and NIH and make his own P&R for coolrunner instead :p
<azonenberg>
fundamentally, they're targeting a different architecture
<rqou>
but it's actually a different algorithm, so it's not like i went and frivolously reinvented it
<azonenberg>
symbiflow is most of the same team behind icestorm/arachne and they seem to be planning to replace it with a new, better tool that will also work on other chips
<buhman>
oh, my (outdated clearly) reading about arachne made it sound like it was unrivaled in performance
<azonenberg>
The new tool isnt usable yet
<azonenberg>
but outperforms arachne in limited testing
<azonenberg>
When done it will be far superior
<rqou>
oh btw azonenberg: i did some poking around and those sbdin/sbdout signals i mentioned the other day appear to be clocking-related?!
<rqou>
as in, the cyclone ii has a primitive with those wires too, but it's on the _PLL_ primitive
<awygle>
buhman: arachne _runs very quickly_ which is probably what you read
<awygle>
but its _quality of result_ is quite poor
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<azonenberg>
interesting
<buhman>
awygle: I thought it was the opposite
<rqou>
wtf quartus
<rqou>
y u so bad at constraints?
<awygle>
I mean, it's fine. it's just that icecube and, apparently, VPR are better
<awygle>
arachne doesn't make any use of timing information in its algorithm for example
<rqou>
it's based on wirelength?
<rqou>
wtf altera
<rqou>
why do some of the JTAG wires have better connectivity than others?
<azonenberg>
explain?
<rqou>
TCKUTAP is only connected to the right-going wire
<rqou>
not the up/down-going wires
<azonenberg>
are the BUFGs to the right? :p
<rqou>
what do you mean?
<azonenberg>
(or whatever altera calls them)
<azonenberg>
The paths from fabric routing to the clock tree
<rqou>
is above
<azonenberg>
ok thats weird
<rqou>
also, a whole bunch of these wires have a connection to the local interconnect of the io tile that it pretends to belong to
<rqou>
but i don't know why this is useful either
<rqou>
because the only way you can go from there is out the chip
<rqou>
anyways, the row io tile structure i'm observing is that a row io tile is made up of 14 muxes
<rqou>
i assume that in the larger chip this usually forms 7 outputs and 7 OEs
<rqou>
in this small chip it forms 4 or 5 outputs/OEs and up to 6 "special" wires
<rqou>
and "special" wires go to the UFM/JTAG
<rqou>
oh, and the clock tree too
<rqou>
so maybe some of these connections are vestigial
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<rqou>
in general though max v is a pretty clean design at a high level
<rqou>
just a giant mess at a detailed level
<rqou>
with all sorts of subtle asymmetry
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<azonenberg>
how would you say coolrunner is?
<azonenberg>
by comparison
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<rqou>
e.g. it's better to put your actual clocks onto GCLK2/3 and to put your global control signals on GCLK0/1
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<rqou>
because GCLK0/1 have better connectivity into the fabric
<rqou>
coolrunner ii seems even more simple, but a bit too limiting to actually do much with
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<rqou>
definitely losing out on the cost-effectiveness too
<rqou>
afaik it's faster though
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<azonenberg>
yeah its not cheap for large ones
<azonenberg>
i meant architecturally
<rqou>
architecturally it's so simple that it's hard for it to be messy :P
<azonenberg>
lol
<azonenberg>
which is why i went with it for babby's first bitstream RE project
<rqou>
the only thing that's a bit weird is the multiple paths into the ZIA
<rqou>
but max v has the exact same thing
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<rqou>
there are actually _three_ outputs from a "macrocell" in max v
<rqou>
max v would have also been okay as a babby's first (LUT-based) bitstream RE project
<qu1j0t3>
pie_: ^
<rqou>
azonenberg: afaik the _worst_ babby's first RE project would be a spartan
<rqou>
xilinx lut architectures always seem like a big mess
<rqou>
with all sorts of "oh, this can't do that"
<rqou>
azonenberg: strategy question
<rqou>
what if after Project Chibi and Project Ravioli (MAX 10)
<rqou>
instead of doing Project Lucoa (Arria that is in the g-sync monitors) maybe we should do Cyclone V?
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<rqou>
Cyclone V has the 6lut/ALM structure too, but it's a lot cheaper
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<awygle>
Do cyclone 10 plz
<awygle>
Also rqou arachne uses Half Perimeter Wire Length as the cost function
<rqou>
hrm, that should be okay?
<rqou>
not sure why i get particularly bad results with it
<rqou>
awygle: gx or lp?
<awygle>
it's not that bad but again, no timing info. also it doesn't bias to reduce longer nets like e.g. QWL
<awygle>
either. I'd prefer GX but that's obviously stickier lol
<rqou>
gx and lp are totally different archs :P
<awygle>
Yeah you told me
<rqou>
ok, we need a new name for this
<rqou>
paging pie_ :P
<awygle>
GX has sweet txvrs tho
<rqou>
pie_: we need something that's a grown up chibi that isn't quite as... big as lucoa :P
<awygle>
I assume you want something dragon maid related?
<rqou>
doesn't have to be
<pie_>
huh what hi
<awygle>
I have thus far avoided that show
<rqou>
i haven't actually watched it
<rqou>
i've only seen clips of kanna :P
<pie_>
me too but there was amusing things on youtube
<rqou>
wait i got it
<pie_>
i might watch it at some point
<awygle>
aren't there always
<rqou>
cyclone 10 lp RE project = Project ⑨
<pie_>
qu1j0t3, hmm
<awygle>
kero kero
<rqou>
since it's kinda a silly part that's just a die shrink of a cyclone iv
<rqou>
so cyclone 10 gx (if i ever get to that) needs yet another name
<rqou>
pie_: "we need something that's a grown up chibi that isn't quite as... big as lucoa"
<pie_>
yeah im thinking
<pie_>
rqou, im not enough og an otaku for this
<awygle>
rqou: name it after suwako (also that song is stuck in my head now)
<pie_>
soon: mughsot lineup of programmable logic as anime girls
<pie_>
lol touhou has like 500 characters right? youd never run out
<pie_>
*mugshot
<rqou>
why don't we have an fpga-tan yet?
<rqou>
azonenberg?
<rqou>
:P
<rqou>
azonenberg: can you ask your $WIFE to come up with one?
<rqou>
pie_: you forget how relevant this is to awygle :P
<awygle>
Whelp I'm out. Between this and a racing game based on Tracy Chapman's Fast Car, it's clearly time to go to bed.
<pie_>
rqou, i dont follow
<rqou>
pie_: berkeley's intro CS course is also SICP-derived
<rqou>
awygle even took the scheme version
<rqou>
i took the modernized python version
<pie_>
hehe
<awygle>
"modernized", "bastardized" who's to say:-P
<rqou>
hey, apparently the CS faculty had extended discussions about this
<awygle>
yeah it was a hot topic for years
<awygle>
according to Harvey
<rqou>
yup
<rqou>
personally i support the view that having a language with the kitchen sink available is better
<pie_>
w-well youre not WRONG
<rqou>
python is imho a more newbie-friendly kitchen sink language than say javascript
<rqou>
afaik only azonenberg here hates it
<rqou>
apparently azonenberg is weird enough that his preferred kitchen sink language is (was?) PHP
<azonenberg>
pie_: $wife has a degree in fine art
<azonenberg>
and spends her spare time drawing furries and pokemon :p
<azonenberg>
(she's not even a furry herself, but apparently it's a good business)
<pie_>
yeah ive heard its good business, its weird
<azonenberg>
rqou: these days i'm more likely to use C than PHP
<azonenberg>
but i still use PHP for quick and dirty text processing or stuff sometimes
<rqou>
pie_: it's thanks to the prevalence of "byuu syndrome" :P
<azonenberg>
like, my "count lines of code in all source files in the current directory and print totals by language recursively"
<rqou>
the condition of being in tech and being trans/furry/weeb/ADHD
<azonenberg>
rqou: lol
<azonenberg>
I was actually just talking about that with some folks at the lab at $work
<azonenberg>
the %age of LGBT folks, and furries, seems vastly higher in tech than the general population
<awygle>
rqou: it's kitchen sink or fit the language in my head after a 90m lecture
<awygle>
I can argue it either way
<rqou>
well, sneklang 61a still did that second part
<rqou>
the "interpreter" project is still a scheme interpreter, hosted in python
<awygle>
I don't agree that's the same and it has other problems but what I was going to say was that they'll probably never actually write scheme in anger now, whereas everybody picks up python eventually.
<awygle>
I think that is a loss. But like I said I can argue it either way.
<awygle>
So *shrug*
<rqou>
yeah i guess
<rqou>
what's much more "fun" is probably cs150 teaching verilog in one 90m lecture :P
<rqou>
(ok, more like 2)
<awygle>
Ugh yes
<awygle>
Although I had some in 61c iirc
<rqou>
not when i took it
<rqou>
they just used that buggy as hell java logic simulator
<awygle>
we used logisim primarily but we had like a lecture on verilog
<rqou>
hmm, i don't think we did
<rqou>
i guess they deleted it
<awygle>
Anyway I wasn't joking earlier, I really am going to bed. Night.
<rqou>
goodnight
<pie_>
awygle, there was an attempt
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<rqou>
wat
<rqou>
the UFM block has a ton of "warning: footgun" going on
<rqou>
azonenberg: "For user-
<rqou>
be tied low if you are not issuing any PROGRAM or ERASE commands."
<rqou>
program or erase operations, but not during read operations. The OSC_ENA signal can
<rqou>
generated logic interfacing to the UFM, the oscillator must be enabled during
<rqou>
so i take this to mean that not enabling the oscillator makes the flash not program correctly?
<rqou>
also "During real-time ISP operation, the internal oscillator automatically enables and
<rqou>
ending of the real-time ISP operation for gated control of this self-enabled OSC output
<rqou>
OSC_ENA signal is tied low. You can use the RTP_BUSY signal to detect the beginning and
<rqou>
outputs through the OSC output port (if this port is instantiated) even though the
<rqou>
condition."
<azonenberg>
tl;dr the UFM uses the OSC for internal self-timing?
<rqou>
yeah of course
<azonenberg>
and i don't think this means that you have to force it off during reads
<rqou>
that's basically stated
<azonenberg>
Just that it must be on for the rest
<rqou>
yeah
<rqou>
but what if you forget?
<rqou>
then it breaks? :P
<azonenberg>
lol
<azonenberg>
i'm actually curious if there is potential to damage the flash by gating the clock at the right moment
<azonenberg>
and moving too much charge or something
<rqou>
you can try that on your own :P
<pie_>
i forgot that the hardware probably has parts without valid state checks
<pie_>
better hope you dont forget those in your compiler software
<pie_>
and i suppose thats an argument for REing the whole thing? :P
<azonenberg>
pie_: oh, almost certainly
<azonenberg>
most fpga routing fabrics have one-hot bits
<pie_>
azonenberg, yeah im pretty sure i asked this before which is why i remembered
<azonenberg>
where if you set them wrong you get bus fights in the fabric
<azonenberg>
i know coolrunner has them
<azonenberg>
i know where, and i've triggered them experimentally (on purpose)
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<azonenberg>
And they do kill the chip, but it takes ~10 mins with every mux bus-fighting at once
<azonenberg>
(have not tested how long a single one takes, or if that's even lethal at all)
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<daveshah>
mithro/tinyfpga: Trellis can already rewrite bitstreams so bitstreams built with Diamond for non SERDES parts can run on the SERDES ones
<daveshah>
Not sure what the legal status of that is though
<daveshah>
Obviously you can't use the SERDES for that either
<mithro>
morning daveshah
<daveshah>
morning mithro
<tinyfpga>
howdy daveshah
<tinyfpga>
I’ll send you one of the new TinyFPGA EX prototypes when I get them built and working
<daveshah>
Awesome
<daveshah>
I'm now looking at timing RE for the ecp5
<daveshah>
Looks like it shouldn't be too bad - other than that it's just a case of figuring out a few remaining tile types (EBR, DSP, etc) but we know the routing for those already
<pie_>
rqou, ill draw an fpga-tan if you can wait long enough for me to learn to draw lol :p
<azonenberg>
i was thinking fpga-chan personally
<azonenberg>
Would there be a CPLD-senpai too? (since product term architectures predate LUTs)
<awygle>
CLPD-nee-sama
<pie_>
apparently -tan is a "lispy" cutesy suffix
<pie_>
(i had to look it up)
<awygle>
yeah tan is just diminutive chan
<pie_>
"classy nee-samas are the best"
<pie_>
sometimes i look back at my discussions in here and think, wow it could be bad if someone took anything i say in here seriously
<awygle>
Gotta be careful stretching the metaphor too far or you end up with ultrascale plus as a very fat baby
<pie_>
hahaha
<pie_>
somehting about buddhas
<azonenberg>
awygle: lool
<azonenberg>
I guess the other option would be to go back to the manufacture/engineering side of things
<azonenberg>
(when will somebody make an anime based on the PCBA schoolgirls? lol)
<rqou>
wtf
<pie_>
probably never, WE have to do it
<pie_>
PCBA?
<rqou>
the ufm block has an address width parameter
<rqou>
the frontend says you must set it to 7 8 or 9
<pie_>
oh ok i just had to google the acronym. yeah.
<rqou>
but then the fitter yells at you if it isn't 9
<rqou>
quality software again
<pie_>
azonenberg, stop saying things like this i dont want to learn animation too
<azonenberg>
pie_: you know the picture i'm talking about right?
<awygle>
rqou: same IP for multiple parts prolly
<pie_>
some people get nerd sniped, i dont. i get subject sniped
<rqou>
all parts in this family have the same size UFM
<azonenberg>
there's two or three from the same artist
<pie_>
azonenberg, yeah theres like 3 and they're between my favorites xD
<rqou>
i like how you had to specifically look for safebooru :P
<pie_>
im not actually sure thats sfw, it just looked like it might be lol
<pie_>
i dont think this artist had and nsfw stuff
<pie_>
*any
<pie_>
maybe we need an ##openfpga-anime channel :p
<rqou>
##openfpga-afterdark :P
<azonenberg>
oh god that would be... a sight to behold
<rqou>
WTF?!
<pie_>
"during the day, you would suspect nothing of these innocent looking programmers"
<rqou>
UFM oscillator to global clocks has to pass through the normal interconnect?
<pie_>
"but at night night they are..."
<rqou>
but why does the mux have a missing setting?!
<rqou>
there must be something screwy going on
<pie_>
rqou, which project is this again?
<rqou>
i think all of these WTFs will need hardware testing
<pie_>
i dont remmeber the names
<rqou>
Project Chibi (MAX V)
<pie_>
ah its not a name
<pie_>
oh well i was going to say ____ has a few screws loose? :p
<pie_>
(inb4 they all have a few screws loose)
<daveshah>
rqou: this sounds a bit like the ice40 tbh
<daveshah>
to go from global clock to output pin, you have to use a feed through LUT
<rqou>
er, you don't here
<daveshah>
still, sounds like there's no direct global connection
<rqou>
this is for the internal oscillator
<rqou>
into the clock tree
<rqou>
not coming out of the clock tree
<daveshah>
oh, I see
<daveshah>
that is stranger
* pie_
off to setting up his server again
<rqou>
in general though ice40 seems to be pretty "altera-like"
<daveshah>
strangely, I heard a semi-insider comment to that effect too
<daveshah>
maybe there was some employee movement to siliconblue
<rqou>
anyways, that mystery bit at the top-left doesn't control the UFM either
<rqou>
i wonder wtf it does
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<rqou>
um...
<rqou>
azonenberg: "WYSIWYG primitive "myufm" has SBDIN port that cannot be connected when the appropriate ini variable is not set"
<rqou>
azonenberg: i wonder what the secret is?
<pie_>
that sounds like bad UI design too?
<rqou>
no, they're hiding something
<pie_>
sure i mean.
<pie_>
the port should not be displayed to the user if they cant use it?
<pie_>
though i suppose when they see tht it exists, in documentation, they will be like "wut why isnt it present" so idk
<pie_>
question, would an pld company make something where unless you put some kind of value in your bitstream it kills the chip? i.e. if you use a different compiler or something
<pie_>
sounds like that could backfire so id guess no
<pie_>
and if its a static value you'd notice during RE anyway, if its nonstatic its a waste of chip space? (and youd find it during RE (?))
<azonenberg>
pie_: they dont expect anyone to use any other chip
<azonenberg>
any other compiler*
<azonenberg>
that's the last thing they expect
<azonenberg>
as far as bad ui design, check out GTPE4_CHANNEL :p
<azonenberg>
hundreds of ports and parameters
<azonenberg>
many of which need magic values not documented naywhere
<azonenberg>
and you just have to use their ip generator
<rqou>
azonenberg: sooo, i figured out what these ports are for
<pie_>
azonenberg, yeah i figured as much
<azonenberg>
oh?
<rqou>
azonenberg: see PM
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<q3k>
01:22:05 azonenberg_work | q3k: you dont even have to be a gun person, magazine pouches are readily available, inexpensive, and fit various kinds of load-bearing gear, velcro, etc
<q3k>
right, that was kind of my point
<q3k>
just being in a country were there's relaxed gun control changes that
<rqou>
wait, are you saying that mass shootings are _not_ normal and can't be fixed with thoughts and prayers?!
<rqou>
/s
<rqou>
<insert the onion article here>
<daveshah>
of course, Europe has far fewer because our thoughts and prayers over here are much better
<rqou>
lolol
<jn__>
older churches => stronger prayers
<cr1901_modern>
We're gonna need those guns for the civil war that starts tomorrow
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<rqou>
:(
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<pie_>
i think jn__ is on to something
<pie_>
US had indians so really its the shamanic stuff they should be doing
* pie_
shakes head
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<awygle>
pie_: in case you're unaware that's literally the plot of American Gods
<pie_>
im ...acquainted? with it
<awygle>
(also Indians live in India, we have native Americans)
<pie_>
i wouldnt khave thought of it if you didnt mention it
<pie_>
heh
<awygle>
Is a good book. I should watch the TV show at some point.
<pie_>
i never actualy understood why they were called indians, but now that you mention it, the story goes that that one dude was looking for india right? so maybe thats it
<awygle>
Yup
<pie_>
guess im a bit slow :p
<awygle>
"Hey its India, nice to meet you, Indians!" "Actually this is a whole other place" ".... Naaaa you're Indians."
<Bike>
not like the taino knew where india was any more than columbus did
<awygle>
Well no but then the joke doesn't work
<Bike>
i think the west indies being where they are is the real joke
<pie_>
meanwhile columbus was thinking "oh shit i better say they're totally indians, my crew is gonna kill me"
<awygle>
You could do another joke along the lines of that thing in Australia(?) where they're called kangaroos(?) because it means "I can't understand you"
<Bike>
i thought that was apocryphal (but hilarious)
<awygle>
Well, sure, but then the joke doesn't work :-P
<awygle>
Such a stickler
<Bike>
wow the language the word is from is called "Guugu Yimithirr"
<Bike>
what a name
<jn__>
in german, there are two words for "indians" (Indianer and Inder), so we can tell them apart
<awygle>
That name sounds like it should be for an Old One
<pie_>
how do you kno wit isnt >.>
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<q3k>
interestingly, in mainstream polish native amricans are still called 'indians'
<q3k>
i don't think I remember a 'native american' equivalent
<q3k>
apart from the generic 'aboriginal' term
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<azonenberg>
q3k: interesting
<azonenberg>
Are you polish?
<openfpga-bot>
[jtaghal-apps] azonenberg pushed 1 new commit to master: https://git.io/f7Yxz
<openfpga-bot>
jtaghal-apps/master 2b473a8 Andrew Zonenberg: Fixed include paths again
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<openfpga-bot>
[jtaghal-cmake] azonenberg pushed 1 new commit to master: https://git.io/f7Ohb
<openfpga-bot>
jtaghal-cmake/master 9d7fc82 Andrew Zonenberg: Updated to latest submodule versions
<q3k>
azonenberg: yes
<azonenberg>
q3k: cool, my family has a lot of ancestry from eastern europe
<azonenberg>
my dad's father was born in poland, his mom was... czech?
<q3k>
i'm sorry? :P
<azonenberg>
Lol
<q3k>
is that where your last name comes from?
<azonenberg>
I believe so, yes
<azonenberg>
We still sing "Sto Lat" at birthday events for that side of the family, although most of us younger folks aren't particularly fluent in polish anymore
<q3k>
heh
<azonenberg>
My dad knows enough that when we had construction done on our house by a contractor who hired lots of polish immigrants
<q3k>
can't blame you for not being fluent, it is a shitshow of a language
<azonenberg>
he was able to understand some of the laborers chatting
<azonenberg>
But would have a hard time holding an extended conversatoin
<azonenberg>
And i just know a handful of words
<q3k>
I've been trying to teach my Romanian girlfriend some Polish and it's pain at every step
<azonenberg>
And lol yes, my european language of choice is German and i'm not super fluent in that either
<q3k>
pronounciation of words is just ridiculous when you think about it
<azonenberg>
but, aside from the gendered nouns, it seems relatively straightforward
<q3k>
declensions are fairly complex
<q3k>
there 7 cases, and quite a few distinct declensions all in all
<azonenberg>
fuuun
<q3k>
conjugation is fairly easy, nothing compared to french
<azonenberg>
Ironic that I picked German, considering that the reason I was born in the US is that my Polish grandfather saw what was going on over the border with Hitler back in the 1930s
<azonenberg>
and decided to GTFO
<balrog>
interesting conversation to drop into :)
<q3k>
well, hisotry is history
<q3k>
keep it in mind but don't let it dictate your life
<azonenberg>
Yeah
<q3k>
i'll be moving to germany within half a year, too
<azonenberg>
These days, the nazis are on the other side of the ocean anyway :p
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<balrog>
sadly they're all over the place at this point :/
<q3k>
there's more naxis in poland than in germany at this point
<q3k>
*nazis
<azonenberg>
i was talking about the us
<azonenberg>
:p
<q3k>
like literal flaming-swastika-in-the-woods-meeting nazis
<balrog>
q3k: yep
<azonenberg>
Actually on topic... somebody needs to make a good f/oss simulator-and-waveform-viewer integration
<azonenberg>
That has the ability to do things like "freeze simulation at time X, poke around a bit in the source, resume sim for another 50 ns"
<azonenberg>
i'm using vivado xsim right now and battling a bug where the displayed hex data in the waveform viewer is simply wrong
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<azonenberg>
all of my rtl makes correct decisions based on that data
<azonenberg>
When i $display() the bus, it looks correct
<azonenberg>
But in the waveform viewer, i see bus[x :+ headers] as changing correctly from cycle N to N+1
<azonenberg>
but bus[0 :+ data] as not toggling
<azonenberg>
if i expand the bus, the bigs look right
<azonenberg>
bits*
<azonenberg>
So only the hex render is wrong
<mithro>
Morning
<q3k>
evening
<daveshah>
evening
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<openfpga-bot>
[jtaghal] azonenberg pushed 1 new commit to master: https://git.io/f7rWW
<openfpga-bot>
jtaghal/master 40e4a5f Andrew D. Zonenberg: build: fixed CMake to link Digilent libs if available
<openfpga-bot>
[jtaghal-cmake] azonenberg pushed 1 new commit to master: https://git.io/f7rWB
<openfpga-bot>
jtaghal-cmake/master 424efae Andrew D. Zonenberg: Enabled Digilent blob detection for CMake build
<rqou>
azonenberg you're using the digilent blob?
<rqou>
not diamondman's code?
<azonenberg>
Correct, i believe his code only works for one particular digilent programmer
<azonenberg>
the blob works with a lot
<azonenberg>
they have some FX* based programmers
<azonenberg>
they have at least two or three FTDI ones with (I think) identical configs
<azonenberg>
at least one PIC based one
<azonenberg>
and they all use different usb protocols
<azonenberg>
I generally use the ftdi blob in preference to the digilent blob for a digilent+ftdi stack
<azonenberg>
at some point i will be adding support for stlink
<daveshah>
The Lattice iceblink have a Digilent programmer with something that's not even one of those iirc
<daveshah>
One of the usb atmegas or something
<azonenberg>
i mean i could totally add a backend for diamondman's code to talk to that one particular digilent programmer without using the blob
<azonenberg>
it would be better than nothing if you want fully open code
<azonenberg>
But it won't add new functionality if somebody has the blob already
<gruetzkopf>
only one of my "stlinkv2" is running ST firmware
<azonenberg>
lol
<azonenberg>
i meant the stlink protocol
<azonenberg>
so i can plug directly to (say) a nucleo and use it
<openfpga-bot>
[jtaghal] azonenberg pushed 1 new commit to master: https://git.io/f7FWg
<openfpga-bot>
jtaghal/master 5925c48 Andrew D. Zonenberg: Reformatted ARM debug messages
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<openfpga-bot>
[jtaghal-cmake] azonenberg pushed 1 new commit to master: https://git.io/f5vaS
<openfpga-bot>
jtaghal-cmake/master 8fa53f1 Andrew D. Zonenberg: Updated to latest jtaghal
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<pie_>
i found this too funny
<pie_>
<Cheery> it is a bit like an impression that PEP is ruining Python.
<pie_>
<dash> Cheery: I guess a more accurate description was "python matured, python-dev did not"
<pie_>
<dash> Cheery: well, it sorta did
<pie_>
shots fired :p
<pie_>
although this is pretty out of context since im too tired to read the scroll
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<qu1j0t3>
scroll is droll
<pie_>
scroll schmoll
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<awygle>
yeah i would love a simulator with real debugging
<awygle>
pause, single-step, etc
<awygle>
(but then i also want that for hardware and nobody seems to think that's useful, so i doubt there'll be a big push on the sim side either)
<sorear>
does that include being able to change the state of flops and memories while it's paused?
<awygle>
ideally, yeah
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<awygle>
_ideally_ ideally, back-propagate that to source :p but that's probably impossible in the general case
<awygle>
i just discovered a library that eliminates about 500 lines of code i've written over the last few weeks. on the one hand - awesome! on the other - dammit!
<sorear>
"eliminates" in the sense of "makes redundant", rather than "malfunctions and destroys"
<awygle>
correct lol
<awygle>
"does the same thing but probably better and definitely in such a way that i don't have to maintain it forever"
<shapr>
awygle: why isn't that useful for hardware?!
<shapr>
awygle: but now you *understand* the library
<awygle>
shapr: i don't know! but nobody seems to think it is. where "nobody" rounds to, like, azonenberg and ZipCPU i guess
<shapr>
I'd certainly want that.
<ZipCPU>
awygle: Which library?
* pie_
adds it to awygle's biggish scale projects list
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<openfpga-bot>
[jtaghal-apps] azonenberg pushed 1 new commit to master: https://git.io/fd0og
<openfpga-bot>
jtaghal-apps/master f57221d Andrew Zonenberg: Tweaked verbosity for jtagclient, added nobanner option to hide startup spam while maintaining high verbosity elsewhere
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<awygle>
pie_: maaaaaaaaaan stop being right about my stupid project list :(
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<openfpga-bot>
[jtaghal] azonenberg pushed 3 new commits to master: https://git.io/fFY8W
<openfpga-bot>
jtaghal/master a14a510 Andrew Zonenberg: Finished initial implementation of multi-device JTAG chain support. Doesn't work with split (pipelined) scans but works fine for normal scans in preliminary testing.
<openfpga-bot>
jtaghal/master 3cced55 Andrew Zonenberg: Minor tweaks to CoolRunner debug tracing
<openfpga-bot>
jtaghal/master 2f49f76 Andrew Zonenberg: Updated all shift operations to use size_t for lengths. Began work on support for multi-device chains.
<azonenberg_work>
rqou: can you test?
<openfpga-bot>
[jtaghal-cmake] azonenberg pushed 2 new commits to master: https://git.io/fFY8B
<openfpga-bot>
jtaghal-cmake/master 14355b9 Andrew Zonenberg: Updated to latest submodule versions
<openfpga-bot>
jtaghal-cmake/master 8fafabd Andrew Zonenberg: build: Enabled symbols for debugging
<rqou>
er, test what?
<rqou>
I'm at work
<azonenberg_work>
When you get a chance
<azonenberg_work>
I have multi-device bypass/pad support in jtaghal now
<azonenberg_work>
So full support, not just enumeration, for arbitrary-sized scan chains
<azonenberg_work>
I use the existing, optimized code path without padding if there's one device
<azonenberg_work>
if multiple, i do a very inefficient bitblt for the padding right now, there's plenty of room to improve performance