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<sorear>
that's what i'm saying, writing a vtr description will hopefully be easier for interested parties than writing a whole toolchain
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<kc8apf>
sorear: everything up to configuration frames is very similar in s6. Big changes are word size is 16-bit instead of 32-bit and frames are a different length.
<rqou>
coupled with 37 unique C4s fuzzed from last time
<rqou>
that's 91 unique inputs
<rqou>
coupled with some unknown number of neighbor LABs
<rqou>
maybe only 5?
<rqou>
that would yield 96 unique inputs for LAB
<rqou>
each LAB has inputs from both the C4 column to the left and to the right
<rqou>
but only inputs from the R4 column that according to the coordinates is above
<rqou>
this further "does not refute" the speculation that rows physically exist in the middle of each tile
<rqou>
rather than between tiles
<rqou>
i am increasingly of the opinion that all fpga RE should in the future begin with die images
<rqou>
and counting all the resources
<rqou>
offtopic rant: i really need to get my father to use better passwords
<rqou>
(yes, despite being a "computer person" he has terrible password habits)
<rqou>
let's just say that most of the passwords are a simple concatenation of two dictionary words and is a very "1990s" password (in the sense that that was when it was first being used, in the sense of the amount of entropy in these words, and in the sense of "words that would be likely to be chosen by a 'tech'-ish person in the 1990s")
<rqou>
(this rant triggered by me connecting a device to the wifi (which i will eventually reconfigure as i work on moving out of berkeley))
<mietek>
any KiCAD experts?
<rqou>
azonenberg is an occasional kicad dev
<rqou>
i've used it but wouldn't call myself an expert
<mietek>
actually I just need someone who’s not a complete noob like me
<mietek>
when editing a part: is it really not possible to edit properties for multiple pins at the same time? e.g. change from input to output
<mietek>
is it really not possible to visualise pin type? e.g. input or output
<rqou>
you can always edit the data files in a text editor :P
<mietek>
thanks for not telling me that it’s open-source and I can also fix it myself
<rqou>
azonenberg: the xilinx die photos on pr0n show rather tall tiles too?
<azonenberg>
rqou: which chip?
<rqou>
hmm maybe i misremembered, let me double check
<azonenberg>
s3 is almost square
<azonenberg>
A DCM and {MULT18x18SIO + RAMB18BWER} are each the same size
<azonenberg>
namely, four CLBs wide and four high
<merskiasa>
Anyone?
<azonenberg>
the aspect ratio of a CLB seems to be about 20% wider than it is tall
<rqou>
merskiasa: sorry, nobody here really uses saleae _that_ much
<azonenberg>
In the XC3S50a...
<azonenberg>
the actual array is 16 wide x 16 high tiles, however one entire block of 4 columns is eaten up by a DCM at the top then three RAM+MULT blocks
<azonenberg>
So the CLB array is 12 wide x 16 high
<rqou>
ok, i'm looking at the protected xc3s50a
<azonenberg>
With a 4x4 cutout at the top just left of center
<azonenberg>
For the second DCM
<azonenberg>
Looking at the RAM/MULT tiles you can see the RAM is at right and the mult is left
<azonenberg>
vs in planahead they're swapped
<rqou>
is this the protected one?
<rqou>
i'm looking at the protected xc3s50 (no a)
<azonenberg>
no i'm looking at the a
<azonenberg>
Then the standard cells in the bottom right are presumably the boot/jtag etc logic
<rqou>
is a vs e vs nothing very different?
<azonenberg>
This is the unprotected azonenberg:xilinx:xc3s50a
<azonenberg>
there are uarch changes, i forget all the details
<azonenberg>
i think they're all the same process
<rqou>
ah ok i was looking at the mcmaster one
<azonenberg>
i have a delayer of the 3s50a on mine
<rqou>
ah so this array is 16x16
<rqou>
i thought it was smaller
<rqou>
ok, so xilinx clbs really are squareish
<azonenberg>
Yes
<azonenberg>
But a CLB is two slices
<rqou>
altera clbs are super tall
<rqou>
wait, so it's CLB->slice->LUT?
<azonenberg>
in older xilinx arches, pre ultrascale
<azonenberg>
a CLB was two slices, each of four luts
<rqou>
and post-ultrascale?
<azonenberg>
One slice per CLB of 8 luts i think
<azonenberg>
The slice is a logical group for some packing stuff, carry chain, and control sets
<rqou>
ah ok
<azonenberg>
So in say 7 series each CLB has two clocks, two set/reset signals, etc
<azonenberg>
one per slice
<azonenberg>
but all ffs in that slice have to use the one clock, the one set/reset, etc
<rqou>
altera doesn't have (in their older archs) this three levels of hierarchy
<azonenberg>
The switch box is dedicated to the CLB
<rqou>
altera just has LAB->LE
<azonenberg>
the other thing is, not all slices are created equal
<rqou>
and altera LABs have multiple control signals and it's a big mess
<rqou>
yeah i do know about SLICEL/M/X
<azonenberg>
in spartan6, there were three types of CLB
<azonenberg>
of slice*
<merskiasa>
https://imgur.com/a/ZPzkJ are the 0V TP4X etc ICSP programming points on this remote? next to the battery
<azonenberg>
Each CLB was a SLICEM plus either a SLICEL or a SLICEX
<rqou>
merskiasa: almost certainly
<rqou>
yeah the xilinx arch seems way more complicated for some reason
<azonenberg>
7 series killed SLICEX, thankfully
<azonenberg>
that was one of the worst decisions they made in spartan6
<azonenberg>
SLICEX had no wide muxes or carry chains
<azonenberg>
Meaning 25% of your chip can't do addition or high fan-in logic
<rqou>
hrm, total unique possible connections C4->LAB varies across tiles too
* awygle
looks at rqou and daveshah, imagines quitting job to hack all day, sighs wistfully
<qu1j0t3>
lol
<daveshah>
awygle: pick a better day job :P
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<awygle>
daveshah: I *like* my job, it just gets in the way of hax
<awygle>
Unfortunately sum(fpga license costs) is not >> my salary
<awygle>
So "pay me to do prjtrellis" for example is not a compelling business case :-P
<daveshah>
solution: embed malware in Diamond, claim Trellis is the only option
<awygle>
Hmmmm
<daveshah>
it is almost certainly possible to come up with an edge case that Diamond fails to synth but Yosys allows
<daveshah>
then say Diamond is blocking your work :P
<awygle>
Lord knows that's true lol
<daveshah>
if you use LSE it certainly is
<awygle>
Doesn't even have to be that edge :-P
<daveshah>
Synplify to some extent, but I haven't really isolated a particular issue per se
<daveshah>
just weird crashes on big/odd designs sometimes
<awygle>
Oh but we use VHDL. Bummer.
<daveshah>
even more work then
<daveshah>
I had a design in VHDL that Diamond synthesised fatally badly
<daveshah>
it was a motor controller state machine, and it optimised away the deceleration part
<daveshah>
checked in every other tool and it was fine, so I'm pretty sure it was a LSE bug
<daveshah>
to be fair, if you buy a verific license, you can use Yosys with VHDL already
<azonenberg>
implr: a bunch of reasons
<azonenberg>
first off, the soc i'm using has integrated ram
<azonenberg>
it's like 5 dies wirebonded on a single substrate (arm, lpddr3, ldo, buck, eeprom)
<azonenberg>
plus 100+ passives
<azonenberg>
If i went with a zynq i'd have to do all that layout myself
<azonenberg>
second, in order to fit the number of GPIOs I need on the FPGA side, while also having a DDR3 bus and another RGMII interface
<azonenberg>
i'd have to go with an xc7z035 in FFG676 or even FFG900
<azonenberg>
or possibly the Z030 in FFG676 but that would really be pushing it
<azonenberg>
The z035 is, i think, not supported by free vivado
<azonenberg>
the z030 is $420 on digikey vs the $260 FPGA + $30 SoC I'm using now
<azonenberg>
A 676-ball FPGA would also use more PCB layers to fan out
<azonenberg>
The brain board is PCB area constrained and the multi-die arm module is significantly smaller than equivalent packaged components
<azonenberg>
Finally, on the security front i dont like zynq's architecture of having the arm be in charge of everything and manage the boot process etc
<azonenberg>
If it was like the old virtex2pro where there was just a cpu thrown off in a corner with the bus going out to fabric, and the cpu didn't have access to the ICAP or anything
<azonenberg>
and i could boot the fpga first without the arm, etec
<azonenberg>
Then i might consider it
<azonenberg>
but i really dont like the way xilinx has the cpu be the boss of everything, i build systems where the FPGA brings up the ARM and not the other way around :p
<pie_>
arm slavery
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<awygle>
azonenberg: you seem like you'd know about ear protection. is there a good solution which blocks *both* high *and* low frequencies?
<azonenberg>
Low frequencies are actually harder because they go through bone conduction etc better
<azonenberg>
Power tools are moderate to high frequency
<azonenberg>
Hammering and gunfire are what i use ear pro for most, which is basically a series of Dirac impulses
<azonenberg>
Super fast rise time single impulse then some ringing after
<azonenberg>
and helicopters too i guess, which is basically a series of said impulses plus turbine noise
<azonenberg>
awygle: what frequency range are you talking about? How powerful is the source / how long are you being exposed for?
<awygle>
it seems like active noise cancelling is good for low frequencies (engine noise, air conditioners) and things like earmuffs are good for higher frequencies (people talking, etc)
<azonenberg>
(And how many dB of attenuation do you want?)
<awygle>
azonenberg: i'm just in the office. i have an air conditioner right above me that oscillates wildly all day and a cubicle neighbor that doesn't understand phone courtesy. i'm not target shooting or anything.
<azonenberg>
ah ok so this is for distraction removal?
<awygle>
i have earmuffs but then it sounds like i'm in a plane, the LF of the AC is constantly rumbling
<awygle>
and i have noise cancelling headphones but then i can hear people just fine
<awygle>
yeah distraction and i'm pretty sure the oscillating AC is bothering my tinnitus
<azonenberg>
Personally, i'd go for a nice set of over-the-ear headphones with active noise canceling plus your music of choice
<azonenberg>
If you just wanted absolute silence, you could go with insertable earplugs and then noise canceling headphones over that
<azonenberg>
Which should give you 30-50 dB attenuation across a very wide frequency band, but i find insertable plugs unpleasant to wear for a long time and total auditory deprivation might get annoying after a while
<awygle>
yeah, i hate insertables :/ okay well, thanks for confirming my options
<azonenberg>
Idea: music with foreign-language vocals
<azonenberg>
a language you don't know, that is
<awygle>
yeah my jpop playlist is invaluable
<azonenberg>
It drowns out the frequency bands of human speech nicely, while not taking much brainpower to process vs a language you know
<azonenberg>
i've become a fan of Ukrainian techno for that purpose
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<azonenberg>
as i know about five words of russian :p
<azonenberg>
But a good set of over-the-ear headphones is helpful too, you'll get some attenuation that way
<azonenberg>
If you have active noise canceling, then just rely on the music to reduce the SNR
<azonenberg>
you should be set
* awygle
scrolls and scrolls and scrolls to get into his budgetary range
<azonenberg>
personally i dont have much trouble working with music going and a relatively cheap pair of Sennheiser HD202's, which are not noise canceling but do fit snugly and block some sound
* kc8apf
has a pair of those I've used at work daily for a few years
<awygle>
kc8apf: things ahead of that on my list - roomba, shop-vac, rack-mount kits, new car
<awygle>
maybe i can talk the company into buying them for me as a bonus or something :p
<kc8apf>
real talk: HD202s are cheap and great.
<awygle>
pie_: what else would you call that? there's moving pictures, and also sound! i can't think of a single thing that could be other than an audio gif
<awygle>
yeah i'm thinking 202s or maybe that monoprice one. i generally like the point on the price/performance curve monoprice occupies.
<awygle>
i don't care that much about the actual _audio_ so *shrug*
<azonenberg>
me and $wife have used hd202s for years, i'm on my second pair after the first broke
<azonenberg>
(fatal accident with a rolling desk chair iirc)
<awygle>
I've never owned a pair of headphones for more than like, eighteen months
<awygle>
I am hard on my stuff apparently
<kc8apf>
awygle: interestingly I've heard that a lot. When I give people a good set of speakers, they suddenly care a lot more.
<azonenberg>
i'm on my second pair since... 2010?
<qu1j0t3>
awygle: i've had my AKG's for.. 13-odd years...
<azonenberg>
of hd202s
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<awygle>
do C ABIs specify struct packing?
<awygle>
i seem to remember that C itself specifies some things but not everything
<kc8apf>
generally struct members will be naturally aligned with padding. pack pragma can force removal of the padding _or_ pad to even longer alignment
<awygle>
hm. don't (e.g.) gcc and clang need to agree on packing though?
<awygle>
in order to cross-link
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<kc8apf>
yes. The defaults are consistent as are the results of applying pragma pack
<kc8apf>
so, messing with packing can break interop but not necessarily ABI
<awygle>
hm, okay. thanks :)
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<rqou>
at risk of causing moar drama, does anybody know why my entire birbsite timeline is currently talking/implying about self-harm?
<Bike>
that chef who killed himself?
<rqou>
ah ok, i guess i didn't hear about that
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<gruetzkopf>
Protip for german-speakers trying to drown out people with music: do not use danish, your German parser will constantly resync and then crash horribly
<gruetzkopf>
(why do I feel like replacing SGIs SPIDER ASIC again (NumalinkII router)
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