* ZipCPU
just built a JSON parser for Yosys outputs .... it wasn't all that hard to do
<sorear>
after the first half of that i was expecting a json parser in verilog
<ZipCPU>
Lol! Thank you sorear, that brought a smile to my face.
<sorear>
(you are aware of azonenberg's verilog protobuf parser?)
<ZipCPU>
Not at all. Care to share?
<ZipCPU>
I was more commenting for azzizi's sake. Indeed, the JSON format was so easy to parse, I'm tempted to build a BLIF parser next. Shouldn't be too hard.
<sorear>
i just know it exists ( https://github.com/azonenberg/protohdl ) and have heard some discussion about it, i don't think i could explain it in detail
<tpb>
Title: GitHub - azonenberg/protohdl: Streaming FPGA/ASIC code generator for Google Protocol Buffers. (at github.com)
<ZipCPU>
Sadly, the readme doesn't tell me much.
<sorear>
yeah, I noticed
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<daveshah>
sorear: I think a JSON parser in Verilog would be easier than the MATLAB one azzizi is suggesting
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<qu1j0t3>
haha
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<aiju>
is there no mailing list?
<awygle>
i don't believe there is a yosys mailing list
<awygle>
would you prefer that over IRC or reddit?
<daveshah>
there's also stackoverflow
<daveshah>
but no mailing list. github issues and pull requests are used for that sort of stuff.