clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
<mithro> Anyone know what the .SEQ_MODE parameter in the output from icetime mean?
* cr1901_modern doesn't know the answer to any of those questions :/
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<mithro> hey cr1901_modern
<cr1901_modern> hello mithro, how's it going?
<mithro> cr1901_modern: Super frustrated because I'm super close to getting things working
<cr1901_modern> mithro: Hey me too! Except the super close to getting things working part
<cr1901_modern> That part has evaded me
<cr1901_modern> I still have crashing lm32 bitstreams on tinyfpga, and I don't know why. I even made a repo documenting crashes
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<mithro> cr1901_modern: At least reproducible is good!
<mithro> cr1901_modern: Want to look at my problem instead then? :-P
<mithro> cr1901_modern: I'm trying to figure out why my icestorm HLC output is not logically equivalent to the input
<cr1901_modern> HLC?
<mithro> Not quite sure what it stands for
<mithro> it's a high level description format that icestorm uses
<mithro> cr1901_modern: You can seen an example here -> https://paste.ubuntu.com/p/JB9TgBD826/#23
<tpb> Title: Ubuntu Pastebin (at paste.ubuntu.com)
<cr1901_modern> Well, if you're intimately familiar w/ ice40 internals, your problem doesn't sound all that fun either.
<cr1901_modern> I wonder if there's a(n easy) way to move _just_ one SB_LUT to another location in a design, and then recompile the result to a valid bitstream
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<xerpi> hi
<tpb> Title: yosys/cmos_cells.sp at master · YosysHQ/yosys · GitHub (at github.com)
<xerpi> the problem is that if I set A to Vdd and B to Vss, then I get "doAnalyses: Too many iterations without convergence"
<xerpi> I'm using ngspice btw
<xerpi> it looks like there's a problem in the node M34 (the one between the nmos transistors in series)
<xerpi> any idea what's going on?
<xerpi> it looks like it's because I'm using different transistor models
* sorear hasn't touched spice in years
<xerpi> hehe
<daveshah> gosh, this takes me back to when I was writing a circuit simulator
<daveshah> just curious, what if you tie A and B via resistors rather than directly?
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<xerpi> daveshah, doesn't seem to work
<daveshah> xerpi: not sure if I can suggest anything more either, haven't touched SPICE for a while either
<xerpi> no worries, I think it's because my capacitance at the output is too small
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<mithro> daveshah: Did something change in yosys recently -- I seem to have lost the ability to get SB_LUT4s in the output?
<mithro> daveshah: Oh - a LUT1 isn't mapped to a SB_LUT4 ?
<daveshah> mithro: What is your code?
<tpb> Title: symbiflow-arch-defs/lut.v at 4mcmaster · mithro/symbiflow-arch-defs · GitHub (at github.com)
<mithro> daveshah: It gets converted to a wire rather than a LUT
<daveshah> Of course it is a wire
<daveshah> That statement is in no way a LUT1
<mithro> daveshah: What is a LUT1?
<shapr> lookup table 1 ?
<mithro> daveshah: Actually - what is the difference between a LUT1 and a wire?
<daveshah> A LUT1 could be an inverter too
<daveshah> Or const 0 or 1
<shapr> neat
<daveshah> If you want a LUT instantiate a LUT
<mithro> daveshah: Is there a specific "LUT1" primitive in Yosys?
<daveshah> There might be an internal one, but you should just use an architecure primitive
<mithro> architecture primitive? As in the SB_LUT4?
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<tpb> Title: Snippet | IRCCloud (at www.irccloud.com)
<mithro> daveshah: Should that work?
<daveshah> Yep
<mithro> daveshah: It doesn't :-( https://github.com/YosysHQ/yosys/issues/567
<tpb> Title: Creating a SB_LUT4 with unconnected inputs causes a C++ exception · Issue #567 · YosysHQ/yosys · GitHub (at github.com)
<daveshah> mithro: clifford will look at it
<daveshah> Bug in the ice40 optimisations
<mithro> daveshah: Yeah
<mithro> daveshah: This LUT implementation kind of looks weird...
<tpb> Title: yosys/simlib.v at 0d636964b81ed5db4a7031a24c4b04e3bc879ad5 · YosysHQ/yosys · GitHub (at github.com)
<daveshah> Not sure, I think it's reasonable
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<Groomblecom> Question about iCE40hx1k devices: how do I write verilog to synthesize a SB_WARMBOOT?
<Groomblecom> As is frequently the case, I found what I was looking for after asking for help: https://github.com/cliffordwolf/icestorm/tree/master/examples/icemulti
<tpb> Title: icestorm/examples/icemulti at master · cliffordwolf/icestorm · GitHub (at github.com)
<Groomblecom> Follow-up question: according to the datasheets, BRAMs are not refreshed when you warmboot, unless you provide initialization data with the new config image. How do I ensure my verilog in each design gets the same BRAM?
<Groomblecom> So that I can, e.g. compute a buffer with one config image, and then warmboot to a second image that processes the first image
<Groomblecom> *processes data from the first image
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<mithro> daveshah: Any idea why icebox_vlog didn't combined the inputs here?
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<daveshah> mithro: Verilog?
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