clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<mattvenn> I remember when I had sram issues with the blackice mystorm board
<mattvenn> I had unstable behaviour on the fpga because the fpga and the sram were both trying to drive the same pins
<mattvenn> because there wasn't enough time for the pin direction to change
<mattvenn> I wonder if something similar is happening with the hyperram on the 8 data pins
<mattvenn> running it slower should resolve it
<keesj> is http://www.clifford.at/yosys/download.html perhaps a bit outdated on ubuntu 18.04 yosys is already in the discto and adding the ppa results in https://pastebin.com/Wt6sdftR
<tpb> Title: Yosys Open SYnthesis Suite :: Download (at www.clifford.at)
<daveshah> keesj: beware that the version of Yosys in ubuntu is very old
<daveshah> I would always recommend building from source following the instructions at http://www.clifford.at/icestorm/
<tpb> Title: Project IceStorm (at www.clifford.at)
<cr1901_modern> I wish my build improvements PR would be accepted... :(
<cr1901_modern> And well fixing yosys-smtbmc to work on Windoze PR too
<keesj> ok
<daveshah> cr1901_modern: clifford's pretty busy right now. ping him again and he'll look at them I'm sure
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<cr1901_modern> Fair enough. It's low priority, I just mainly wanted to knock off a few bullets off my todoist :P
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<mattvenn> well slowing it down makes it behave. And I think I might be right about the ram and fpga both driving the same lines at once
<mattvenn> here's clk, data and direction at 3mhz system clk = 0.75mhz ram clock
<mattvenn> and this one is when the serial breaks and things start going crazy.
<mattvenn> 6mhz = 1.5mhz ram clock
<mattvenn> you can see the bidirectional signals now have intermediate levels
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<mattvenn> so my question is, how can this part be used with the h40 chips at higher clock rates?
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<ZipCPU> What is icetime giving you?
<mattvenn> 90mhz
<ZipCPU> And it's only working successfully at 6mhz?
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<mattvenn> 0.75mhz it seems to work
<mattvenn> anything higher than that and the fpga and the sram both try and drive the inout lines at once
<mattvenn> which them seems to result in strange behaviour
<ZipCPU> Hmm ... sounds like the controller is buggy. Is there an output enable wire? Are you watching that one?
<mattvenn> I think I need to take another step back
<mattvenn> I still have problems with the serial comms event at this low speed
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<elms> daveshah: I'm adding ability to track symbols in hlc. Any opinion on hlc syntax? I was thinking "wire .sym> symbol" (eg "span4_y1_g7_1 .sym> vec0[1]")
<daveshah> elms: haven't really worked with hlc
<daveshah> I agree symbols are a good idea, that seems a reasonable enough implementation
<elms> That's good enough for me to create a PR. Thanks.
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