clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<cr1901_modern> Well, operation "squeeze yosys into small amount of RAM" failed LOL
<tpb> Title: William D. Jones: "Well, this is never something I want to see LOL..." - Mastodon (at mastodon.social)
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<TD-Linux> is that your router
<sorear> Adjacent toots suggest an old rpi
<TD-Linux> wow one of the 256MB ones
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<sorear> Armv6 so…
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<awygle> needs swap space
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<cr1901_modern> BSD disklabel makes it difficult to add swap I think
<cr1901_modern> In any case, yes it's an original Model A Pi
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<cr1901_modern> So anyways,aAccording to SystemVerilog Annex C, defparam is a candidate for deprecation. Does anyone know of an alternate way to set parameters within a module hierarchy that doesn't involve "parameterizing every single parameter for every submodule at the top level"? (I'm guessing the answer is "no", but still curious...)
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<lutsabound> No. I don't know any other way.
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