clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<promach_> ZipCPU: you mean even if the trace does not show that it failed, it is still due to bugs in my code ?
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<ZipCPU> promach_: How long is your trace?
<ZipCPU> Nevermind ... it's an induction failure.
<ZipCPU> I have never seen an example of a design failing induction that didn't show the error in the trace.
<promach> ZipCPU: let me check through my code again. sigh, multiclock induction needs more debugging than the normal single-clock induction
<promach> ZipCPU: wish me luck in finding out the bug !
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<ZipCPU> promach: I think I recall telling you before you started your multiclock induction proof that my own multiclock proof of a serial port was the hardest proof I had done.
<ZipCPU> Perhaps you need to try proving some simpler things and come back to multiclock later, once you've learned to trust the tools more.
<promach> ZipCPU: I trust the tool !!! ;)
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