<montjoie>
search for dma_map_single for example in Linux source
<montjoie>
so you need to do what do DMA API, flush the cacheline
<montjoie>
chrisf_: if you do DMA, you need to use the API for it:)
<chrisf_>
montjoie: seems my H5 problems are because I haven't implemented dma_map/unmap. If I put my descriptor in SRAM C the length error goes away :)
2017-08-04
<montjoie>
sun4i-ss with dma is slower (/10)
<montjoie>
note also that sun4i-ss is cpu driven, not dma like sun8i-ce
2017-07-31
<wens>
oliv3r: on A31+, only 1 and 8 are supported. If you ask for 4, the DMA driver will give an error
<wens>
oliv3r: it's not the RX/TX DMA, but rather the DMA burst length
<oliv3r>
RX_DMA that is
<oliv3r>
wens: you mean that i2s gained dma support in 4.11+ with i guess a quirk for sun6i, but that was not backported?
<wens>
whats funny is that it will not work without it's preceding patch from mainline, as the DMA burst length is not supported on A31/A33
2017-07-26
<wens>
it's just a couple of registers to set the audio format and stuff, and a FIFO for dma
2017-07-25
<cafijo>
Now I loaded: usbnet 17700 0 - Live 0x00000000 vfe_subdev 4695 0 - Live 0x00000000 vfe_os 4113 1 vfe_subdev, Live 0x00000000 cci 21858 0 - Live 0x00000000 videobuf_dma_contig 5567 0 - Live 0x00000000 videobuf_core 16528 1 videobuf_dma_contig, Live 0x00000000 sunxi_schw 13015 0 - Live 0x00000000 (O) mali 205592 20 - Live 0x00000000 (O) lcd 38016 0 - Live 0x00000000 disp 995816 7 lcd, Live 0x00000000 nand 282678 0 - Live 0x00000000
<wens>
montjoie: see commit f4458b92d2 ("net: stmmac: Adjust dump offset of DMA registers for ethtool") in netdev
2017-07-18
<mripard>
you're going to spend more time programming the DMA engine than getting your data out of the FIFO
<mripard>
it won't make much sense to use DMA for such small data transfers
<Net147>
the Allwinner BSP code doesn't use interrupts or DMA at all
<Net147>
oliv3r: and possibly DMA
2017-07-10
<wens>
there's also DMA (wink)
2017-07-06
<oliv3r>
Net147: with cma and cma_dma enabled on your branch i've got it working now
2017-06-09
<wens>
montjoie: do you remember who it was that noticed the DMA descriptor stuff for sun8i-emac was compatible to dwmac?
2017-06-06
<montjoie>
it is why I never submitted DMA patch for it
<montjoie>
sun4i-ss with DMA is unusable
<montjoie>
perhaps its DMA
2017-05-06
<jernej>
MoeIcenowy: I received mali450-gles-linux-x11-dma_buf-no_Werror driver from Steven, but it's same old story with license
2017-05-03
<wens>
montjoie: maybe DMA can't keep up?
2017-04-22
<MoeIcenowy>
(after dma_set_mask
<MoeIcenowy>
mripard: so this is really only 32-bit capable -- thus what should I do to convert dma_addr_t to uint32_t?
2017-04-19
<wens>
and sun8i_dwmac_reset should be sun8i_dwmac_dma_reset
2017-04-02
<MoeIcenowy>
"Support for USB, DMA, and Ethernet are in the works"
2017-03-19
<BenG83>
on most of my work projects I have one SPI bus with 4-5 devices on it like ADCs or DACs that do DMA transfers once set up
<BenG83>
how does it handle multiple chipselects? do you have to do that manually regarding DMA transfers?
<willmore>
MoeIcenowy, so expect delays, but it's very DMA efficient. ;)
<willmore>
MoeIcenowy, 1 means DMA after one transfer or 1 left?
<willmore>
MoeIcenowy, (looking at your SPI code) is the max transfer length due to the DMA or some other reason?
2017-03-10
<montjoie>
do someones here get some "DMA-API: cpu touching an active dma mapped cacheline" randomly on H3/A64
2017-02-25
<wens>
KotCzarny: the display hardware does dma to stream and composite layers or framebuffers together
2017-02-22
<MoeIcenowy>
the sentence in U-Boot is "fb_dma_addr = gd->fb_base - CONFIG_SYS_SDRAM_BASE;"
<MoeIcenowy>
search for "fb_dma_addr = " in sunxi_display.c
2017-02-06
<MoeIcenowy>
C.H.I.P. also released a r6p0 dma-buf libMali blob suitable to be used with sun4i-drm driver in mainline.
<Ke>
dma-buf is afaik preferred solution for newer kernels
<Ke>
I think you'll need libmali, ump or dma-buf and mali-drm
2017-01-26
<MoeIcenowy>
mosajjal: are your binary dma-buf ones?
2017-01-23
<MoeIcenowy>
but I remember mmc seems to have also a direct DMA that do not pass DMA controller?
2017-01-21
<Net147>
rellla: you can try CONFIG_CMA=y, CONFIG_CMA_SIZE_MBYTES=256, CONFIG_DMA_CMA=y
2017-01-20
<ssvb>
the only reliable way to implement support for SPI messages larger than the FIFO size is to use DMA
<rellla>
[ 0.000000] Reserved memory: created DMA memory pool at 0x43d00000, size 80 MiB
<MoeIcenowy>
[ 0.000000] Reserved memory: created DMA memory pool at 0x000000004a000000, size 96 MiB [ 0.000000] OF: reserved mem: initialized node cma, compatible id shared-dma-pool
<montjoie>
MoeIcenowy: yes more dedicated since dma register are different
2017-01-19
<codekipper>
yeah...but I'm not sure if DMA is working yet
2017-01-15
<willmore>
If DMA worked and long transfers worked and the clock could get up to 32MHz, then 4MB/s--4 seconds to read the whole chip.
2017-01-09
<montjoie>
like sun4i-ss with DMA
2017-01-04
<apritzel>
beeble: can't we use DMA for sending a loop of some characters?
2016-12-26
<montjoie>
the probe seems good, now I need to populate dma functions
2016-12-17
<apritzel>
MoeIcenowy: you can pass through pure MMIO, but no DMA
2016-12-12
<apritzel>
MoeIcenowy: the SDHC2 controller can only cope with 8K of DMA at once, not with 64K as the other two
<apritzel>
apparently it is somehow connected to some DMA and/or DDR-RAM, but how remains unclear
2016-12-10
<maruel>
in particular page 158 of file:///home/maruel/Downloads/micro/Allwinner%20R8%20User%20Manual%20V1.1.pdf implies it should be possible to get a dedicated DMA to do it for you
<apritzel>
maruel: are you talking about the Allwinner DMA controller, as in @0x01C02000
<maruel>
mripard: forgot to mention, my testing is currently on CHIP/R8. I've been testing only reading for now and suspect the DMA writes 0xFF in dst on failure, since the DMA has no register to mark that a failure occured.
<maruel>
I've wrote my own DMA driver and confirmed it to work by copying data across two physical pages
<maruel>
mripard: hi, I see from the logs that you stated on 2015-04-10: 14:32 <mripard_> you can't drive the GPIOs with DMA.
2016-12-02
<codekipper_>
I was hoping to test it on my pine64 but no dma yet
2016-12-01
<montjoie>
starting to really modify stmmac, not easy, all dma_ops need to be rewritten, some core file also
2016-11-29
<apritzel>
the DMA buffer size is limited to 8K on that MMC2 controller (and only there, MMC0 & MMC1 can take 64K)
2016-11-26
<wens>
either way the DMA description handling structure is the same, and same goes for the register bits
2016-11-24
<MoeIcenowy>
but sun6/8i have a different DMA engine
2016-11-15
<victhor__>
hi. I'm wondering, is it possible to use TVDAC to output arbitrary values, from, say, DMA? instead of only being able to output encoded video from the framebuffer. I don't think I have been able to find TVDAC documentation, on the H3 datasheet at least...
<wens>
codekipper: in addition, the dma controller is subtly different from a31, in that the dma burst length register is offset by 1
2016-11-14
<montjoie>
strange A64 is getting DMA timeout for PRNG/SHA384/SHA512
2016-11-06
<Net147>
MoeIcenowy: you need CONFIG_CMA=y, CONFIG_CMA_SIZE_MBYTES=256, CONFIG_DMA_CMA=y for X11 otherwise buffer allocations in sun4i-drm may fail
2016-11-05
<Net147>
wens: thanks that fixed it - CONFIG_CMA=y, CONFIG_CMA_SIZE_MBYTES=256, CONFIG_DMA_CMA=y
2016-11-03
<wens>
plaes: don't get your comment on the dma patch :p
2016-10-28
<ssvb>
slapin: switching to DMA-BUF needs a bit more work
2016-10-24
<MoeIcenowy>
oh A64 DMA is different from A33...
2016-10-20
<mripard>
X + dma-buf
2016-10-17
<montjoie>
but I need to sent it, DMA is so so slow that I prefer hwrng come first
<montjoie>
no the problem is that if I send a day the patch for enabling DMA, I have a problem on how to handle the lock
2016-10-12
<wens>
dr1337_: recording should be easy, it's just a matter of the capture dma and the capture audio paths
2016-10-11
<MoeIcenowy>
are you familiar with DMA?
<MoeIcenowy>
(current SPL NAND driver used A10 DMA engine in a hard-code way
2016-09-08
<GeneralStupid>
for example we delive an architecture without DMA because the lateny is smaller then
<wens>
technically the tcon can also draw ram content, but it needs the system dma controller to feed it data
2016-09-06
<jmcneill>
wens: our driver switched between dma and pio mode, the pio data register is at a different offset in a31 and later
2016-09-01
<_mamalala>
KotCzarny: according to the tables there, in most cases it is faster to varying degrees ... however, i'm rather baffled that it becomes so incredibly slow as soon as dma is used ....
2016-08-09
<wens>
the old ones are just direct dma into the codec
2016-08-05
<oneinsect>
or mali400 with dma-buf
2016-07-29
<montjoie>
apritzel: oh you do it but after dma_mapping_error
<apritzel>
montjoie: I used this to test a similar fix for the MMC driver (which also uses DMA descriptors) on my BPi-M1
2016-07-20
<jonkerj>
but those dma_ops seem to be something for ARM64 only
2016-07-17
<Wizzup>
I recall that vanilla didn't have dma yet for spi, but I guess that doesn't matter, and may be outdated
2016-07-14
<apritzel>
MMC and EMAC have an "integrated DMA engine"
<MoeIcenowy>
mmc dma do not need main dma engine?
<apritzel>
MoeIcenowy: sure, but that's a different DMA for MMC (and EMAC)
<MoeIcenowy>
A64 have still no DMA Engine support
2016-07-13
<MoeIcenowy>
apritzel: I think there may be some issues about DMA
<xEBIx>
vpeter: Yes I did that in config already, but I am unshure what is needed elsewhere to make that option work. Is CMA related to DMA or do I not need that for that option to work?
<xEBIx>
Maybe CMA != DMA?
<xEBIx>
Hello, I have some trouble with loading Kernel Moludes in 3.4.104+. This ERROR: "ERROR: 256 KiB atomic DMA coherent pool is too small!" But I did have this in the config "CONFIG_CMA_SIZE_MBYTES=4, CONFIG_CMA_ALIGNMENT=8, CONFIG_CMA_AREAS=7" shouldnt that set CMA to 4M′?
<mripard>
wens: IIRC, we had to change the frequency of AHB(?) to 300MHz for DMA to operate properly
2016-07-05
<boob-wrt>
wens : i pick up your pll2 clk on my H3, better than my hacked pll2 but always issue in dma desc. I hope it's related to miss configure analog part. i have i/o error when i "alsactl init 0" and no mixer available
2016-07-04
<codekipper>
boobwrt: maybe dma but there all sorts of things in your code that looks odd. The analog stuff isn't regmaped like normal..it needs to be manipulated
<boobwrt>
codekipper : yes i have compiled dma_sun6i=y in my build, maybe outdated?
<codekipper>
boobwrt: have you built dma into your build?
<boobwrt>
wens : happy to see devs on audiocodec :) I stuck on dmaengine when i play with H3 audiocodec (Null pointer) on create struct dma_async_tx_descriptor pointer
<wens>
great, now have to debug the dma driver :(
<wens>
invalid dma configuration... wha?
2016-07-03
<wens>
dmabuf is the mainline way of passing around dma buffers
2016-06-21
<montjoie>
Amit_T: see my v2 branch, dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
<montjoie>
the only call added for 64bit is the dma mask
2016-06-17
<ssvb>
lennyraposo: we need to get the mali blob first, the change from UMP to DMA-BUF will require some updates to the code
2016-06-13
<wens>
MoeIcenowy: it's probably normal, since the reset controller is probed after dma
<MoeIcenowy>
"sun8i-a23-r-pinctrl 1f02c00.pinctrl: Reset controller missing" and "sun6i-dma 1c02000.dma-controller: No reset controller specified"
2016-06-12
<MoeIcenowy>
NFC_REG_o_EFNAND_STATUS NFC_REG_o_PATTERN_ID NFC_REG_o_MDMA_ADDR NFC_REG_o_DMA_CNT doesn't exist in sun7i but exist in sun8iw5
<bbrezillon>
well, IO_DATA is only needed for DMA accesses
<bbrezillon>
and AFAICT, it's the same IP with some extra features like 'bitflips in erased page detection', or 'dedicated DMA interface'
2016-06-08
<apritzel>
one is guarding DMA and DRAM
2016-06-03
<ssvb>
KotCzarny: even if you don't plan to use mali, you still could have the DMA block of some hardware unit competing with the CPU sometimes
2016-05-24
<mripard>
lennyraposo: dma_buf comes for free with GEM if you don't do anything weird and/or stupid
2016-05-23
<lennyraposo>
3. The KMS portion on the DRM driver related to display (DE, TCON, HDMI hardware related) needs Allwinner engineerign team to implement. The GEM portion coding can achieve by dma_buffer method, whcih is easy to accomplish.
<lennyraposo>
2. Need to use dma_buffer method to implement USER layer and DRM driver.
<lennyraposo>
they are apparently working on a DMA Buf implementation
<codekipper>
tkaiser: I only work with mainline....with the dma patches now in I think we've enough to test with
2016-05-12
<montjoie>
apritzel: 4 channel of DMA task (8 if I can use also the Secure CE)
2016-05-11
<montjoie>
KotCzarny: the A83T and H3 is only with DMA (no cPU poll) so no choice it will free CPU
2016-05-08
<montjoie>
but I fear that DMA will never be usable, I need to confirm it, but the data coruption bug made DMA impossible
<KotCzarny>
montjoie: those tests with dma mention its much slower
<montjoie>
longsleep: KotCzarny SS do not use DMA for the moment so always CPU...
2016-05-07
<Amit_t_>
If a cache line size is greater than that of dma desc structure size , would it be problem with recv buffers
<Amit_t_>
apritzel: ok, You want me to have, __aligned attribute against struct emac_dma_desc rx_chain[CONFIG_TX_DESCR_NUM] ?
<ssvb>
and because DMA-BUF is a standard thing in the mainline kernel now, ARM has eventually changed their code to use DMA-BUF instead of UMP
<ssvb>
UMP was invented as a necessary solution at the time when DMA-BUF did not exist yet
<lennyraposo>
3. The KMS portion on the DRM driver related to display (DE, TCON, HDMI hardware related) needs Allwinner engineerign team to implement. The GEM portion coding can achieve by dma_buffer method, whcih is easy to accomplish.
<lennyraposo>
2. Need to use dma_buffer method to implement USER layer and DRM driver.
<lennyraposo>
3. The KMS portion on the DRM driver related to display (DE, TCON, HDMI hardware related) needs Allwinner engineerign team to implement. The GEM portion coding can achieve by dma_buffer method, whcih is easy to accomplish.
<lennyraposo>
2. Need to use dma_buffer method to implement USER layer and DRM driver.
2016-05-05
<Amit_t_>
Also if I don't DMA desc struture to cache line size I do see ERROR: v7_dcache_inval_range - stop address is not aligned - 0x7bf47650 messages
<Amit_t_>
apritzel: Hello, Just wanted to check that is it required to have DMA desc aligned to cache line size for cache ops to perform ?
2016-05-03
<apritzel>
Amit_T: also a driver does make certain assumption, like no pending DMA transfers, for instance
2016-04-29
<montjoie>
Amit_T: when the hardware sent a frame it then go the next descriptor (the 4*u32 structure). you can see it in TX_DMA_CURR_DESC
<montjoie>
the DMA TX state will let you know if DMA is stopped and why
<montjoie>
Amit_T: try restart dma after each packet and print DMA STATE register
<bbrezillon>
plaes: nand support on sunxi platform is almost ready (I recently added DMA support, which improves perfs)
2016-04-25
<ssvb>
the odroid/exynos people have been using the DMA-BUF flavor of mali for a while, so we can use some of their code
<ssvb>
the reference code from ARM for the DMA-BUF mali flavour is xf86-video-armsoc
<lennyraposo>
got news that allwinner is going to provide some binary for DMA Buffer
<apritzel>
does the OPi U-Boot run with caches enabled? I guess you would need some cache maintenance then for the EMAC DMA buffers ...
<lennyraposo>
Allwinner is building the Mali DDK DMA Buffer and not UMP
2016-04-21
<KotCzarny>
unless calling dma is slow and bottlenecking
<bbrezill1>
I recently optimized raw perfs by using DMA in the sunxi NAND driver
2016-04-20
<montjoie>
no use of external DMA device
<montjoie>
the DMA is done by EMAC, so it is reseted/asserted in the same time
<montjoie>
DMA reset ?
<Amit_T>
montjoie: we don't do DMA reset and assertion in H3 emac driver, it is not required ?
2016-04-14
<plaes>
DMA and that notice patch should be enough
<montjoie>
when tx_stop_queue raise, try to increase nbdesc_tx and for rx_dma_ua try increase nbdesc_rx and see if perf raise also
<montjoie>
rx_dma_ua
<montjoie>
wens: I am interested in the other stat counter like rx_dma_stop and tx_stop_queue
2016-04-13
<lennyraposo>
Fixed sunxi-gmac integer overflow for DMA address when system has more than 1GB
2016-04-08
<KotCzarny>
jelle: does it use dma etc or just churn data all the time?
2016-04-07
<ssvb>
and the buffers management (ump, dma-buf, ion, cma and a bunch of other buzzwords) kept changing over time, but that's just a minor annoyance because the basic principles are all the same
2016-04-05
<nieuwbie>
[ 0.634900] sun4i-dma 1c02000.dma-controller: No clock specified
<montjoie>
:( a tx timeout appears, but the trace seems to say that tx_dma_start variable is dangerous
2016-04-04
<montjoie>
the design of setting a bit (dma can work on this) and the same bit at 0 said it is sent is bad
<ssvb>
but a much better solution for fast scrolling is some sort of DMA acceleration
<ssvb>
the display controller scans out the framebuffer via DMA
2016-04-03
<longsleep>
aha at the end it is just a simple int overflow .. they are returning dma addresses as int while they are unsinged long really - if its loo large booom!
* montjoie
need to re-read DMA doc
<montjoie>
interesting the dma_single problem since I use it for sun8i-emac...
2016-04-02
<lennyraposo>
dma_(whatever) _single needs to be changed
<pulser>
hmm interesting longsleep - that would indeed explain it. It should be possible to force this to use memory < 1 GB for DMA I assume?
<longsleep>
aha, i think it is a sunxi-gmac.c issue after all - it is using dma_*_single which according to the docs cannot use HIGHMEM, thus it crashes when there is more than 1GB RAM - if i understand it correctly that is
<tkaiser>
longsleep: I wonder why the crashes only happen with Ethernet on the 2GB models. Isn't there anything else using DMA?
<pulser>
I wonder if the issue is as "simple" as some offset in the 2 GB config for the DMA coinciding with high addresses of RAM?
<longsleep>
pulser: ok, i assume mainline U-Boot also properly sets 2GB into FTD and thus will crash on DMA as well
<longsleep>
So, the Pine64 2GB model boots up with 2GB with booti, bot only with 1GB when booting with boota both using the exact same Kernel image and all. When booting with 2GB, Kernel crashes when doing any DMA (like ethernet). Full crash log at http://paste.ubuntu.com/15580185/ - if anyone wants to help give me a ping
2016-03-30
<wens>
also getting RE-RUN RX DMA sometimes
2016-03-24
<codekipper>
wens: have you played with DMA for your recent A31 patches
<codekipper>
both complain that "set_config line 510 COOPS Invalid DMA configuration src mb 0 dst mb 4"
<montjoie>
the only DMA work I do is on the crypto engine
<montjoie>
my DMA patch for audio ? not me:)
<codekipper>
Hi, I've brought in your dma patches onto my sun6i build.
<codekipper>
do you have those patches for dma handy?...I've failed to find them.
2016-03-22
<montjoie>
in which page ? since H3 have only DMA it will be async
2016-03-21
<ssvb>
montjoie: yes, without DMA usage it is hard to blame DRAM
<montjoie>
ssvb: and no DMA yet since my last test show me again some "DMA timeout"
<ssvb>
montjoie: I looked up a bit, and if I understand it correctly, the crypto code does not use dma yet?
2016-03-18
<ssvb>
one takes the mali kernel driver and hooks it with the display driver via DMA-BUF, job done
<ssvb>
that's why the mali kernel driver has support for UMP buffers in the older versions and DMA-BUF support in more recent ones
2016-03-14
<KotCzarny>
and something about reworking dma code
<longsleep>
i think its related to DMA
2016-03-13
<GeneralStupid>
i dont get why wa consumes so many cpu when there is a dma controller
<GeneralStupid>
tkaiser: but thats not "DMA" related or is it?
<GeneralStupid>
but dma should really be used...
<premoboss>
so it seems cpu is doing pulling, no irq, no dma
2016-03-09
<plaes>
DMA patches fix this issue, but there was also another patch that fixed the non-DMA case
<plaes>
gusenkovs: mainline sun6i doesn't support DMA
<gusenkovs>
In sun6i spi support DMA or not support DMA? If sun6i spi support dma send register #define SUN6I_DMA_CTL_REG ? #define SUN6I_DMA_CTL_RF_READY ? #define SUN6I_DMA_CTL_TF_NOT_FULL ? #define SUN6I_CTL_DMAMC_DEDICATED ?
<gusenkovs>
In sun6i spi support DMA or not support DMA? If sun6i spi support dma send register #define SUN4I_DMA_CTL_REG ? #define SUN4I_DMA_CTL_RF_READY ? #define SUN4I_DMA_CTL_TF_NOT_FULL ? #define SUN4I_CTL_DMAMC_DEDICATED ?
2016-02-27
<ddc>
Not sure if it is something to do with DMA
2016-02-26
<plaes>
do you remember why the sun4i SPI DMA patches were previously denied?
<plaes>
gah.. I sent out some spi dma fixes but forgot to CC linux-sunxi :S
2016-02-21
<longsleep>
well i think i got DMA
<longsleep>
apritzel: DMA for sound?
<apritzel>
well, I briefly looked at it the other day and you need DMA, don't you?
<diego71>
KotCzarny: true, but I never seen strong correlation between cpu speed and sata performance, so I don't think is a problem of dma in A20.
<KotCzarny>
diego71: some chips have proper dma that isnt affected by cpu clock
2016-02-13
<plaes>
ah.. it was DMA that sucked
2016-02-08
<wens>
allwinner's code seems to imply usb otg dma is fixed on a33 and later
2016-02-07
<_aeris_>
and CONFIG_ZONE_DMA_FLAG is not settable
<_aeris_>
i don’t have ZONE_DMA on vanilla kernel :(
<apritzel>
well, there is ZONE_DMA_FLAG and USB_OTG
2016-02-05
<KotCzarny>
dma is the bottleneck then?
<catphish>
KotCzarny: well its better than half duplex, but not as fast as full duplex, i'd suggest the DMA bandwidth is about 200MB/s
2016-02-04
<KotCzarny>
is dma controllable/configurable at all?
<catphish>
it only works on DMA
<KotCzarny>
can you do it without dma?
<catphish>
to clarify, the GMAC (Ethernet) is working entirely on DMA
<KotCzarny>
mem reads? any dma?
<catphish>
KotCzarny: my current theory is that DMA is slow at reading data from DRAM, but i have literally no evidence for this
2016-02-03
<catphish>
i'd still like to learn more about the sun7i gmac dma, but i'll look at those other products too, they look like nice dev boards
2016-01-31
<catphish>
i suspect my question is silly and there are a handful of reasons, all beginning with "you're doing it wrong", i'll learn more about the DMA tx process
<catphish>
i guess theres a lot of DMA options to tune :)
2016-01-30
<plaes>
DMA controller
<KotCzarny>
hrm, why is dma not used? /sys/devices/platform/sunxi_dmac/dma/*/bytes_transferred all 0
2016-01-22
<mripard>
MoeIcenowy: audio and DMA
2016-01-19
<KotCzarny>
then there is no/partial dma being used, which means cpu has to do more work than required
<KotCzarny>
tkaiser, bad dma? cpu waiting for some io?
<KotCzarny>
because 100-200M/s from hdd and 100% cpu usage might be an indicator of dma not being used
<KotCzarny>
wens, so even if there is no indication, reading from disk/network uses dma and not cpu only?
<wens>
KotCzarny: those have their own built-in DMA engine, not using the system wide one
<KotCzarny>
hmm, is dma used for gmac/sata/mmc/anything on bpi? (m1 or r1)
2016-01-18
<apritzel>
how big are our DMA buffers? they may happen to fit in the cache ...
<catphish>
well i'm happy then, i know where to put my pagetable, my stack and my code, the only thing that wont fit in sram is my ethernet dma, but thats fine in dram
<catphish>
i want to map it so i can disable caching on peripherals and DRAM (since i only use it for DMA reads), and enable for SRAM, and also enable the icache (which i dont believe needs the MMU)
2016-01-17
<catphish>
the dma ethernet is ideal for my specific case
2016-01-14
<catphish>
apritzel: so far just receiving, but now i understand how the memory structure and DMA works, i shouldnt have too much trouble expanding it
<catphish>
i read the GMAC initialization code in u-boot, it was much simpler to understand than the linux driver, so i'm working through that, just got stuck when it came to deciding where to put the DMA buffers
<catphish>
apritzel: i'm primarily interested in Ethernet DMA right now, can this be pointed to SRAM, or DRAM? or either?
<catphish>
i don't know if I will need DRAM or not, depends somewhat on how the GMAC DMA works
<catphish>
i'll go read more about how the DMA works, and where i should be putting my DMA Ethernet buffers
2016-01-13
<apritzel>
(that's the difference between dma_addr_t and phys_addr_t in Linux)
<catphish>
am i right in thinking that the OS gives the NIC a memory location to use? i've never worked with DMA before
<apritzel>
catphish: I guess it's safer to disable RX/TX before booting Linux, as it avoids spurious DMA or interrupts
2016-01-12
<apritzel>
they seem to heavily ignore the fact that they are different types of addresses (dma_addr_t, phys_addr_t, long, void*)
<mripard>
montjoie: sun8i_dma_interrupt ?
2016-01-10
<apritzel>
montjoie: OK, by now I rewrote good parts of their BSP driver (partly to appease checkpatch), fixed some bugs on the way and found some undocumented bits (like bit24 in the 2nd DMA descriptor word)
2015-12-19
<BorgCuba>
no UMP required, it uses something called "dma-buf"
2015-12-18
<tkaiser>
But I would assume it can be a clock source thing, DMA or simply a few lines of code?
<tkaiser>
Nope, the A20's SATA implenentation (or drivers? or DMA?) is quite a bit limited. More than 45 MB/s write and 200 MB/s read I've never achieved
2015-12-13
<MrBar>
what about gpio speed with dma?
2015-12-11
<wens>
a80 even has a separate dma controller for it
2015-11-29
<montjoie_>
interesting the a64 datasheet, the emac is the same as h3 but with heavy copy/paste, since dma regsiter take 32bit address
2015-11-23
<nove>
mripard: i want a tool, that can even work when the kernel is corrupt, by a incorrect dma transfer
2015-10-02
<a1d3s>
something under dma was to enable
2015-09-22
<montjoie>
but all my tries fail with DMA never ending, or worst, bad transfer
<montjoie>
but I convinced that playing with DMA engine DDMA_PARA_REG register could boost something
<montjoie>
probably like a "minimal len for dma"
<montjoie>
for disk encryption, using DMA give speed/4
<mripard>
but being fast has never really been the point of a DMA controller
<mripard>
it doesn't really surprise me, the DMA engine is not really fast
<montjoie>
<horror> I have updated my bench for AES 128 on http://sunxi.montjoie.ovh/ with DMA results for the security system</horror>
2015-09-16
<montjoie>
for the moment no, I need to finish DMA support
2015-09-15
<semlanik>
But DMA engine is small part of platform support
<Wizzup>
Support for DMA engine"
<semlanik>
Because DMA is part of basic "platform support" that looks like is not ported to mainline yet
<semlanik>
Is there someone who is working on DMA?
<db2601799>
Anyone has any suggestions in what area to look at regarding performance issues related to a GMAC using external PHY (like stmmac to b53) - PCB distance is one, but i'm thinking a DMA or TOE could have an impact on buffering?
2015-09-13
<wens>
well there's no way you could merge dma support for a platform specific device driver if you can't test it, so the dmaengine driver comes first, then the peripherals
<wens>
Wizzup: the musb driver does not support dma on sunxi yet
<Wizzup>
I was a bit confused because dma support was merged, but not yet hooked up to the driver I guess
<Wizzup>
Ok, I guess the only option is to tell the driver to fall back to using no dma, since no dma option is avail
2015-09-06
<Wizzup>
Isn't the DMA engine mergined?
2015-09-03
<oliv3r>
Michal is a little reluctant to have it merged, because with 4.3 we have SPI-DMA support
2015-09-01
<wens>
bpi-user: they have their own internal dma engines connected to the memory bus, and don't use the SoC's
<bpi-user>
wens: Thanks for your reply earlier today. You wrote, DMA is only used by uart/spi/crypto/audio. What about USB and Ethernet? The A20 manual also mentions USB and Ethernet in the register descriptions for the DMA engine. I'm not used to reading datasheets, so maybe I get it all wrong. But can USB and Ethernet make use of the DMA driver as well?
<mripard>
it's even often the opposite, with DMA being slower than the CPU to transfer data
<mripard>
montjoie_: DMA has never been a guarantee of performances
<montjoie_>
bpi-user the DMA need to be used by driver, for example I am writing the support for it in crypto, but for the moment very bad performance
<wens>
audio seems to require dma
2015-08-28
<RSpliet>
oliv3r: what can you tell this chap about upstream sata support? does the controller (really?) have it's own dedicated DMA engine?
<RSpliet>
TheLinuxBug: well, there is the matter of DMA, you might want to specify your kernel so someone else might be able to tell you more about it :-P
2015-08-25
<ssvb>
mripard: do you mean the dma stuff?
<pirea>
wens so 4.3 will have support for dma-slave only?
<uncle_gonzzo>
emilio lopez send the patches for sun4i-dma. And in slave dma is only the patch for the dma-slave. The other patches emilio posted weren't applied.
<uncle_gonzzo>
i saw that the dma patch in next doesn't include the dts file changes could someone add these patches into sunxi-next?
2015-08-07
<oliv3r>
but the diff-stat for hans's tree is really small; dma + audio stuff, usb power and nand stuff atm
<oliv3r>
wens: I take it the only major difference now in hans's sunxi-wip and maxime's sunxi-next is the dma stuff and the sound stuff?
2015-08-03
<montjoie>
Good news The Security System DMA seems to work now
2015-07-31
<mripard>
DMA might
2015-07-30
<enrico_>
dma=y, codec=m
<ignatenkobrain>
CONFIG_DMA_SUN4I
2015-06-15
<nove>
rellla: if that is the case, it means another dma transferrer to read the frames