Turl changed the topic of #linux-sunxi to: Allwinner/sunxi /development discussion - did you try looking at our wiki? https://linux-sunxi.org - Don't ask to ask. Just ask and wait! - https://github.com/linux-sunxi/ - Logs at http://irclog.whitequark.org/linux-sunxi
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<wens> codekipper: https://github.com/wens/linux/tree/wip/a31-audio this is where i am atm
<wens> ssvb: i meant i'm only familiar with the vanilla mainline kernel, and not various distros
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<MoeIcenowy> wens: you get only sound from the left?
<MoeIcenowy> is the sound a mix of left and right
<MoeIcenowy> or the sound is just left and right is muted?
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<wens> MoeIcenowy: it's something wrong with how DAPM is dynamically enabling various switches
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<codekipper> wens: thanks for that....I'll try it when I get home
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<mripard> wens: there is exactly when the script I gave you shines
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<wens> mripard: i know, it does wonders :)
<wens> mripard: the diagram it gave looks correct, but the registers aren't
<mripard> weird
<mripard> is it in the regmap debugfs file ?
<wens> i used regmap debugfs to dump the registers, and they aren't right
<wens> fyi the bits that aren't correct are specified in the DAPM widgets, not kcontrols
<mripard> ok, so it's really DAPM
<wens> so i'm thinking maybe there's something wrong or limiting in the dapm topology engine
<mripard> not regmap caching policy
<wens> the diagram looks like this: http://wens.tw/dapm.pdf
<mripard> it looks correct
<wens> but only "Right DAC" and "Left Output Mixer" register bits are enabled, instead of both left/right channels
<mripard> do you have your code somewhere ?
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<wens> i see you want to start adding clocks using the clk-sunxi-ng for the old SoCs? piece by piece maybe?
<mripard> yes
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<wens> ok
<mripard> there's no point in merging new old-style clocks
<mripard> except maintaining dead code :)
<mripard> but I don't really want to do that
<wens> just bug fixes i suppose, if we still have bugs in there
<mripard> yes, of course
<wens> i hacked up the old clk driver to get something working
<mripard> hmmm
<mripard> +#define SUN6I_CODEC_OM_DACA_CTRL_DACAREN(31)
<mripard> +#define SUN6I_CODEC_OM_DACA_CTRL_DACALEN(31)
<mripard> is it expected ?
<mripard> that it's the same value?
<wens> (facepalm)
<mripard> and you have the same thing for the mux the line below
<mripard> that might explain ;)
<wens> yeah, i think i was half way through adding controls, then got interrupted
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<wens> only issue left is that the "source switch" controls don't flip for both channels at the same time
<wens> that and the board has left/right wired in reverse :(
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<wens> damn, found a bug in dapm :(
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<boob-wrt> wens or mripard : do you know if there is an other way that dapm to configure alsa control? Because in header i don't find a way to execute a user function to get or set value in small memory (8bit x 25)
<boob-wrt> wens : i pick up your pll2 clk on my H3, better than my hacked pll2 but always issue in dma desc. I hope it's related to miss configure analog part. i have i/o error when i "alsactl init 0" and no mixer available
<boob-wrt> it seem this function "SOC_SINGLE_BOOL_EXT("Audio lineout", 0, codec_get_lineout, codec_set_lineout)," is available in mainline kernel and in some codec driver...it's can run external function but how configure widgets and routes? :)
<wens> the header is the wrong place to look
<wens> look at how other drivers are written
<wens> unfortunately there is no real documentation for ASoC
<boob-wrt> i just look in soc-dapm.h to see if other way exist
<boob-wrt> yes anyway thanks for sharing your progress it help a lot
<wens> the _E variants are what seem to allow you to specify an event handler
<wens> not sure how it works the other way around, if you want something like jack detection
<wens> mripard: codekipper: my branch is updated to the first proper working version
<boob-wrt> yes i see something to enable HP to activate gpio
<boob-wrt> i will try to progress with this handler event, it 's look like a good idea
<boob-wrt> if there is an easy way to pass data (vol, gain) in handler
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<wens> boob-wrt: why would you pass (vol, gain)?
<wens> you sound like you are hacking the analog bits in with one event handler
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<boob-wrt> because it's in little memory and it 's not directly a register available from regmap
<wens> you can write a custom regmap for it
<wens> then assign the regmap to the codec
<wens> it is much cleaner this way
<boob-wrt> :) out of my knowlege!
<wens> learn :)
<boob-wrt> i discover regmap 2 day ago :)
<wens> for a basic regmap you only need to define read/write functions, and some other configs, like the register range
<wens> see the regmap setup bits in drivers/bus/sunxi-rsb.c
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<boob-wrt> yep i will study it
<wens> wha?
<OverCR> now that was unexpected
<KotCzarny> uh-oh
<KotCzarny> little evil gone eviller
<OverCR> not the best idea leaving design and SDKs to AW
<KotCzarny> maybe they just need cheap submanufacturer with some brand name and connections
<KotCzarny> or just want to proliferate that area at all cost
<KotCzarny> Allwinner will design the reference designs and work on the SDKs
<KotCzarny> buahaha
<KotCzarny> good joke
<KotCzarny> sad part is that they could succeed, who wouldnt want cheap lte tablet
<OverCR> business is business I guess
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<codekipper> wens: cheers
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<MoeIcenowy> mripard: to be honest, I do not like sunxi-ng clock driver
<MoeIcenowy> I still think small and flexible clock drivers are better
<MoeIcenowy> especially when introducing new soc support
<mripard> you've not spent enough time working on the clocks then
<mripard> having the exact rate you want is very difficult to get right with the composite and basic clocks
<mripard> and you have to do it in each and every driver
<mripard> and I don't see what's different about the introduction of a new soc
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<luoyi> mripard: https://github.com/linux-sunxi/linux-sunxi/commit/04c85ecad32a28c4afde7e088237075ab6aec0be does this means that the m1 plus dts patch has been accepted by the sunxi community ?
<mripard> yes
<MoeIcenowy> mripard: so now should we introduce new clock drivers for old SoCs with clock-ng?
<mripard> and will be part of 4.8
<mripard> MoeIcenowy: only lists the new clocks you want in the soc file
<mripard> call of_iomap instead of of_io_request_and map
<mripard> and that's it
<luoyi> mripard: and does the i2s parent clock patch has been merged in 4.7 ?
<wens> mripard: or we could change the old clk driver to use of_iomap (in places where we had of_io_request_and_map)
<mripard> wens: yeah, I don't know, that would probably impact all SoCs
<mripard> and I don't really want that
<MoeIcenowy> mripard: is r16 just a rebrand of a33?
<mripard> yes
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<tuxillo> hi
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<wens> codekipper: you are using lineout?
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<codekipper> wens: I believe so....justed changed the routing in your code to add it
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<wens> according to the reference design, lineout would have an external speaker amp, and 2 gpios to control it (one is shutdown , the other is mute)
<codekipper> ok...let me look at the i7 fex.
<wens> though it seems to work if you just leave it floating
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<boob-wrt> wens : can you confirm that your regmap tip is something like : make a bus with write/read and create an "scodec->regmap_analog_bus = regmap_init(&pdev->dev, bus, &pdev->dev, &sun8i_codec_regmap_analog_config)" or something in this direction?
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<wens> yeah
<wens> but you would probably do that in the prcm driver, then export it as a syscon
<boob-wrt> good point to know :)
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<MoeIcenowy> wens: how to use syscon in dt?
<wens> haven't used it before
<MoeIcenowy> so do I :-(
<MoeIcenowy> I found some PheonixSuit firmware of Colorfly E708 Q1, and added them to http://linux-sunxi.org/index.php?title=Colorfly_e708q1
<MoeIcenowy> but I'm afraid that someone will not understand the Chinese of Baidu NetDisk...
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<MoeIcenowy> wens, mripard, or others: can you test my axp20x-battery driver with *real* axp20x?
<MoeIcenowy> I have currently no devices with axp20x
<MoeIcenowy> but only axp22x
<MoeIcenowy> Have anyone bought Pine64 from Aliexpress or Taobao?
<MoeIcenowy> (Although I know they're fake
<MoeIcenowy> (However, are they really using H64
<MoeIcenowy> (or they're at least exact board copy?
<wens> i do not have a battery hooked up
<MoeIcenowy> wens: what a pity
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<rellla> omg
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<wens> ?
<rellla> unteachable
<MoeIcenowy> rellla: there're always users not so clever as developers.
<MoeIcenowy> (There're always also some users more clever than developers, and then a part of them will be develoeprs
<rellla> MoeIcenowy: It's not the "not so clever". It's the "do everything but not what one suggests, that wants to help"
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<ssvb> rellla: in my experience, a surprisingly high percentage of such guys have a PhD degree :-)
<ssvb> rellla: stubborn, cocky and dismissing any helpful advices just because they are of course much "better" than any person trying to help them
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<codekipper_> wens: Thanks..I've now got audio out of my I7
<codekipper_> looks like the audio socket is headphones and not lineout
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<OverCR> I just got my first UART set-up working, yay
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<codekipper_> spdif is now working on A31. I'll bag up some patches asap.
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<|Jeroen|> yay my C.H.I.P has finaly arrived
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<buZz> |Jeroen|: woot!
<buZz> my pocketchip still isnt shipped ;(
<|Jeroen|> looks nice
<|Jeroen|> i plugged it in on usb and a minute later i could open a serial connection over the usb
<|Jeroen|> 2 commands and its on the wifi
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<buZz> :) they spent a couple months finetuning that debian install
<buZz> it better be easy :P
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<|Jeroen|> yeah nice it runs a simple debian, i might just leave it on there
<|Jeroen|> Linux chip 4.3.0-ntc
<buZz> as long as they keep it updated :P
<buZz> else we'll just burn their office down
<buZz> ^_^
<|Jeroen|> lol
<buZz> there is #chipsters btw
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<|Jeroen|> they seem to have a web based app to load new images onto it
<|Jeroen|> ah nice thx
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<plaes> buZz: most of the chip is mainlined
<mripard> plaes: but not the NAND :/
<buZz> yes
<mripard> so you can't boot from the storage
<mripard> which is bad
<plaes> it will be eventually
<mripard> indeed
<mripard> but it might take some time
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<|Jeroen|> mhz, how does it then boot?
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<mripard> on mainline ? It doesn't, which was the point of the discussion :)
<|Jeroen|> ah, it thought it was running mailine
<|Jeroen|> since it was 4.3
<|Jeroen|> thought the other sunxi linux was only 3.1 or somthing
<mripard> it's a mainline-based kernel
<mripard> but we have a number of patches on top
<mripard> including the one to deal with the NAND
<|Jeroen|> ah ic
<mripard> that we merge into mainline, but it's a slow process
<plaes> ah.. it is this SLC hack?
<mripard> the SLC hack is one of the patches yes
<mripard> proper MLC support in UBI is another bunch of them
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<MoeIcenowy> mripard: I've heard from bbrezillon and rgwan that the SLC hack won't be merged...
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