<MoeIcenowy>
montjoie: rx and tx delays is always a disaster ;-)
<MoeIcenowy>
but are they present on sun7i-a20?
<wens>
yes
<jelle>
MoeIcenowy: bananpi has it iirc
<jelle>
*bananapi
<wens>
see bananapi r1
<MoeIcenowy>
I remembered it
<BenG83_PB>
is that not a PHY rather than a SoC question?
<wens>
BenG83_PB: the delay lines are in the SoC
<BenG83_PB>
ok
<montjoie>
MoeIcenowy: dwmac-sun8i have it (board bpi m3 need it)
<MoeIcenowy>
wens: I didn't find the delay set in sun7i-a20-lamobo-r1.dts
<wens>
it is in the glue layer around the dwmac core
<wens>
MoeIcenowy: it's in U-boot, because the old dwmac-sunxi driver doesn't support it
<MoeIcenowy>
so it
<MoeIcenowy>
so it's set and kept in u-boot?
<wens>
yup
<wens>
we should update the bindings for the old stuff once dwmac-sun8i is merged
<wens>
and also get rid of the nasty gmac* clk
<montjoie>
wens: dwmac-sunxi and sun8i are incompatible, perhaps I read you wrong
<MoeIcenowy>
I think the gmac* guy is really something belong to GMAC block but set in CCU/syscon
<MoeIcenowy>
montjoie: have you checked EPHY issue?
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<montjoie>
MoeIcenowy: not yet
<montjoie>
will trytoday
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<wens>
montjoie: the clock related settings in the syscon are the same
<wens>
montjoie: just that they are in the CCU (perhaps because it looks like a clock)
<MoeIcenowy>
and in R40 it's in CCU again
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<MoeIcenowy>
wens: how do you think to export this word to gmac driver?
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<MoeIcenowy>
a syscon with size 0x4?
<MoeIcenowy>
(I mean the CCU one
<wens>
not sure
<wens>
not in a hurry either
<wens>
device tree binding would just be a phandle pointing to the CCU i suppose
<MoeIcenowy>
will need this for R40 ;-)
<MoeIcenowy>
but really not a hurry ;-)
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<MoeIcenowy>
as I have even no wired network access -- I'm testing MAC drivers with a Ethernet wire directly connected to my laptop ;-)
<wens>
using the syscon implementation in the kernel is not going to work properly
<wens>
there's no locking with respect to the CCU driver
<MoeIcenowy>
will start to continue on DE2 DRM driver...
<wens>
probably export a regmap from the CCU driver, then have the gmac driver use of_find_device_by_node + dev_get_regmap
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<NiteHawk>
libv, turl: linux-sunxi.org out of disk space again?
<NiteHawk>
Warning: Unknown: Failed to write session data (files). Please verify that the current setting of session.save_path is correct (/var/lib/php5) in Unknown on line 0
<NiteHawk>
Warning: Unknown: write failed: No space left on device (28) in Unknown on line 0
<NiteHawk>
(at the bottom of wiki pages)
<wens>
plaes: are you going to do a20 CCU driver?
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<MoeIcenowy>
jernej: do you have any explaination of magic numers in sunxi_composer_mode_set ?
<MoeIcenowy>
jernej: seems that only one channel can be used at one time?
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<Turl>
NiteHawk: looks like so
<Turl>
NiteHawk: I've cleaned the apt caches to give it breathing space
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<Turl>
libv: if you can take a better look later that would be great, I need to leave in a min
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<NiteHawk>
Turl: thx!
<plaes>
wens: thinking about this... ;)
<plaes>
but I'm quite busy during this month
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<MoeIcenowy>
finished a sun8i_mixer.c based on sun4i_backend.c
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<MoeIcenowy>
building sun8i-modified sun4i-drm driver
<rellla>
\o/
<rellla>
MoeIcenowy: so on mainline effort page moinejf should be replaced?
<libv>
oh, and here we thought we had solved that
<libv>
Turl: will do
<MoeIcenowy>
rellla: after I send some patch
<MoeIcenowy>
I wish moinejf will someday re-appear and send a v8 ;-)
<rellla>
i think he dropped his efforts ...
<rellla>
MoeIcenowy: will your patch include hdmi bits?
<MoeIcenowy>
nope
<MoeIcenowy>
I will develop my patchset first on a V3s, which have only one pipeline ends with LCD controller
<libv>
Turl: after you cleaned the cache, all is well, it seems
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<libv>
we have a third of the disk available
<MoeIcenowy>
maybe unlinked pictures should be cleaned
<libv>
i think the cache just became too large
<MoeIcenowy>
yes it's possible ;-)
<libv>
it's been ages since we last had a problem with our tiny /
<libv>
6 months at least
<MoeIcenowy>
sun8i_mixer.o passed build ;-)
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<plaes>
libv, Turl: do we have backups? ;)
<rah>
the sunxi_defconfig includes a "sunt4_ts" driver but my .fex points to an EDT FT5406 and there's an edt-ft5x06 driver for it but that isn't included in sunxi_defconfig
<plaes>
I guess you are aware what happened Gentoo wiki
<rah>
s/sunt4_ts/sun4i_ts/
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<plaes>
rah: then it needs to be added
<rah>
what does the sun4i_ts driver do? and do I also need an edt-ft5x06 driver?
<plaes>
in case your tablet uses edt-ft5x06 touchscreen, then you need it
<libv>
plaes: i've been told "yes", but i have no details
<rah>
plaes: how come it's not included in the sunxi_defconfig?
<rah>
plaes: there seem to be a few .dts files that have an EDT FT5406
<rah>
s/.dts files/sun4i .dts files/
<MoeIcenowy>
sun4i_ts is for the integrated *resistive* touch screen controller
<MoeIcenowy>
if you board uses a capative touch screen, thus it won't fit your board ;-)
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<willmore>
MoeIcenowy, good luck!
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<alex_s_>
Hi, my cubietruck shows only u-boot screen on CRT-monitor but no kernel messages or login. With older u-boot/kernel combination it shows me the whole boot process and then a login. Via uart I can see the whole booting process. How can I enable the simple-framebuffer again? I'm on uboot 2016-11 and mainline 4.10.0
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<willmore>
libv, Turl how big is the wiki's data? Any easy way to export a backup? Do you see any value to that?
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<willmore>
Hmm, the mediawiki site makes it look pretty easy.
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<MoeIcenowy>
I got my DE2 drm driver running on a V3s SoC with a LCD panel!
<Wizzup>
:)
<rellla>
MoeIcenowy: congrats
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<MoeIcenowy>
mripard: I think there's a bug at sun4i_backend.c in function sun4i_backend_update_layer_buffer: paddr is a address started at 0x40000000, but de_be wants a address started at 0x0; it works because no A13/A33 device come with more than 1GiB memory
<MoeIcenowy>
is there a way to gracefully get a memory address started at 0x40000000?
<MoeIcenowy>
s/0x40000000/0x0
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<huawei>
MoeIcenowy, what board?
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<libv>
willmore: it's amazing how many people find the sunxi wiki that valuable
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<libv>
i had 3 seperate persons at fosdem state how great it is
<libv>
and i just heard the same in #coreboot
<libv>
it does seem pretty valuable
<libv>
now, at my previous customer, we ended up running a clandestine machine under my desk, to provide us with a wiki
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<libv>
and we did daily backups, of the database to the standard xml file, one line per change, and then stored the result in git.
<libv>
it was lightning fast, tiny, and reliable
<MoeIcenowy>
huawei: LicheePi Zero
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<libv>
i will introduce that, on top of whatever else we have, as it worked truly great
<MoeIcenowy>
it's the only board that I have and have TCON0's raw RGB exported
<MoeIcenowy>
it have a 40-pin RGB LCD panel port
<MoeIcenowy>
but tomorrow I may get a Pinebook to make this driver more useful ;-)
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<shadeslayer>
MoeIcenowy: oooh nice
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<shadeslayer>
libv: hey, are you the guy behind armbian?
<shadeslayer>
ah no, confused you with someone else :P
<libv>
no, i am the guy behind modesetting, free ati drivers, first native coreboot display driver, open arm gpus, and making the sunxi wiki that useful
<shadeslayer>
:D
<shadeslayer>
thanks for the sunxi wiki indeed :D
<libv>
i also ended up paying for the sunxi server, as mnemoc was paying it out of his own pocket and it is a business expense for me
<shadeslayer>
I still haven't figured out why my kernel doesn't boot though
<libv>
there's quite a few great sunxi community members who keep it that useful though
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<AneoX>
Hi to all! Does anyone have some experience with a A20 uart on speed > 1.5mbps ? I have success run it on 2mbps, but not with all my boards. 2 of 4 boards works nice, but another 2 is glitching
<MoeIcenowy>
yes it only took me several hours to work it out, although I have at least 3 times of failed trials ;-)
<wens>
still only half(?) way through my drm cleanup + support multiple pipeline work
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<MoeIcenowy>
wens: have you read my DRAM position issue said several hours ago?
<wens>
something about 0x40000000 vs 0x0?
<MoeIcenowy>
yes
<MoeIcenowy>
the current sun4i_backend.c writes address started at 0x40000000
<MoeIcenowy>
but what is wanted is address started at 0x0
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<MoeIcenowy>
maybe you will discover some problem on A31 boards with 2GiB DRAM
<wens>
where is that?
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<MoeIcenowy>
sun4i_backend_update_layer_buffer
<wens>
not sure what the problem is?
<MoeIcenowy>
the paddr is finally started at 0x40000000
<MoeIcenowy>
you can try this code
<wens>
[ 2.109401] [drm:sun4i_backend_update_layer_buffer] Using GEM @ 0x7be00000
<wens>
[ 2.109408] [drm:sun4i_backend_update_layer_buffer] Setting buffer address to 0x7be00000
<wens>
[ 2.109414] [drm:sun4i_backend_update_layer_buffer] Setting address lower bits to 0xdf000000
<wens>
[ 2.109421] [drm:sun4i_backend_update_layer_buffer] Setting address high bits to 0x3
<wens>
still not sure what the problem is?
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<MoeIcenowy>
how many DRAM is present on your board?
<wens>
1G
<MoeIcenowy>
0x7be00000 is beyond 1G ;-)
<wens>
dram starts at 0x40000000
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<MoeIcenowy>
the address to be written should be the physical address in DRAM, not the logical address seen by CPU
<MoeIcenowy>
you can check sunxi_display.c in u-boot
<wens>
really?
<wens>
my framebuffer works fine though
<mripard>
we're using the physical address already
<mripard>
and 0x7be00000 is around 958MB
<wens>
MoeIcenowy: 0x7be00000 _is_ the physical address
<mripard>
so below 1G
<MoeIcenowy>
search for "fb_dma_addr = " in sunxi_display.c
<MoeIcenowy>
DE_BE (and DE2) see DRAM start at 0
<MoeIcenowy>
the sentence in U-Boot is "fb_dma_addr = gd->fb_base - CONFIG_SYS_SDRAM_BASE;"
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<wens>
yes it still works?
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<MoeIcenowy>
wens: it still works as we have 512MiB or 1GiB DRAM
<wens>
guess it's because dram access wraps around
<MoeIcenowy>
so that DRAM will loop in its address space
<MoeIcenowy>
yes
<MoeIcenowy>
I tested on V3s DE2 -- V3s have only 64 MiB DRAM, at it first comes with a value 0x43b80000 (or some number near it)
<wens>
in that case, please send a patch to fix it
<wens>
however it seems this is not needed on the a80
<MoeIcenowy>
A80 DRAM starts at 0x20000000 but not 0x0, right?
<wens>
yup
<MoeIcenowy>
so maybe it's still needed...
<wens>
and allwinner kernel does not do the subtraction
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<MoeIcenowy>
so what we need is to do experiment on a real 2GiB DRAM board
<wens>
that bit is #ifdefd for sun8iw1, sun8iw3, sun8iw6
<MoeIcenowy>
w6?
<ssvb>
MoeIcenowy: it's a matter of *bus* vs. *physical* addresses, apparently some Allwinner SoCs have need a correction to convert between them and the others don't
<MoeIcenowy>
w6 is DE2...
<wens>
uh, correction, last one is sun6i
<MoeIcenowy>
what's w1? a20?
<wens>
w3 i think is a23
<wens>
a31
<ssvb>
MoeIcenowy: physical address - how the CPU sees memory, bus address - how a peripheral sees it
<MoeIcenowy>
ssvb: thx ;-)
<MoeIcenowy>
so the needed SoCs are only A31?
<MoeIcenowy>
(A23 have only 1GiB address space
<MoeIcenowy>
(sorry, I mean it can only address 1GiB DRAM
<ssvb>
MoeIcenowy: for example, on A20 this correction is needed, but not on H3 anymore
<MoeIcenowy>
jernej: have you did experiments on boards with 2GiB DRAM?
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<MoeIcenowy>
at least on A64 it's needed -- my Pine64 is 2GiB version ;-)
<ssvb>
MoeIcenowy: we can realistically detect the difference only on boards 2GB RAM, because with just 1GB the problematic bit is in the unused address line
<MoeIcenowy>
after I got Pinebook, I will make DE2 DRM support for A64
<MoeIcenowy>
A64 uses the first pipeline with RGB interface (although then a bridge is connected)
<ssvb>
MoeIcenowy: so what is the starting address of DRAM as seen by DE2 on H3? 0x00000000 or 0x20000000?
<MoeIcenowy>
0x00000000
<MoeIcenowy>
if jernej's U-Boot HDMI driver can run on boards with 2GiB DRAM
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<ssvb>
s/0x20000000/0x40000000/
<MoeIcenowy>
oh one of my friend used it on a OPi Plus2, which have 2GiB DRAM
<MoeIcenowy>
so surely it's 0x0
<ssvb>
MoeIcenowy: are you really sure about this?
<MoeIcenowy>
sure, as the U-Boot HDMI driver for DE2 does the -0x40000000
<ssvb>
then it probably works in a different way for Mali
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<wens>
maybe these devices that have dram gates access dram directly through the dram controller, as opposed to through the system busses?
<MoeIcenowy>
DE2 do not have DRAM gate
<MoeIcenowy>
at least on H3/A64/H5/V3s
<MoeIcenowy>
oh I must go sleep for tomorrow's meeting with TL Lim and Allwinner guys
<wens>
catch up tomorrow
<rah>
in a number of a10 .dts files there are entries for the USB ID and detection GPIO pins on the OTG interface but there seems to be some redundancy:
<rah>
ssvb: I saw the second one but not the first, thanks
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<rah>
ssvb: I don't understand though; the pinctrl-0 nodes seem to be states, in which case what's the point of adding state descriptions to something which is using the (input) pins to detect state? :-)
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<rah>
ssvb: or perhaps a more direct question: what *is* the difference between the usb0_id_detect_pin and usb0_id_det-gpio?
<rah>
and usb0_vbus_detect_pin and usb0_vbus_det-gpio?
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<ssvb>
rah: I may be wrong, but first we need to initialize the pin (set the correct function, such as gpio input), then we need to use it (actually read the pin state to retrieve the necessary information)
<rah>
ssvb: I see, I guess that makes sense
<BroderTuck>
rah: you working on the pengpod?
<rah>
BroderTuck: I am yes, I saw what you said before
<rah>
I have a mainline u-boot and mainline linux running on it
<rah>
it's a minimal .dts at the moment though, so I'm adding bits
<BroderTuck>
rah: nice, I have only an old 3.4 build running on mine
<rah>
maybe it will get better soon :-)
<BroderTuck>
do you have the 1st or the 2nd version? mine is the second, with 8188eu wifi
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<dossalab>
Hey guys, what rootfs can I use at board with a13? I have some errors with archlinux "Unable to handle kernel NULL pointer dereference at virtual address 00000018"
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<MoeIcenowy>
apritzel: when will you make your LPDDR3 support code?
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<apritzel>
MoeIcenowy: is the embedded DRAM in the V3s LPDDR(2) as well?
<MoeIcenowy>
not LP
<MoeIcenowy>
but DDR2
<apritzel>
ah, OK
<apritzel>
too bad ;-)
<MoeIcenowy>
but it said that the next batch and the productive batch of Pinebook is LPDDR3
<MoeIcenowy>
and what I will get is such a LPDDR3 one ;-)
<apritzel>
yes, I know
<MoeIcenowy>
(he says that I will be the first one to get this batch ;-)
<apritzel>
I was just hoping that you had some LPDDRx support in your series already ;-)
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<apritzel>
MoeIcenowy: so the "mixer" in the DE2 is what is left of the G2D?
<MoeIcenowy>
nope
<MoeIcenowy>
G2D is G2D.
<MoeIcenowy>
it only co-exists with DE2 in R40 ;-)
<MoeIcenowy>
I chose the module name in BSP's lowlevel source code's de_clock.c
<apritzel>
ah, OK, so mixer is a completely different term then?
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<MoeIcenowy>
yes
<apritzel>
MoeIcenowy: so I just started with staring at the boot0 disassembly again...
<MoeIcenowy>
I think someone implemented LPDDR3 support?
<apritzel>
MoeIcenowy: in U-Boot?
<MoeIcenowy>
yes...
<apritzel>
MoeIcenowy: for Allwinner DRAM?
<MoeIcenowy>
for SoPine
<MoeIcenowy>
I think I saw it several days ago.
<apritzel>
MoeIcenowy: mmh, can't find anything
<apritzel>
MoeIcenowy: do you have a pointer?
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<apritzel>
MoeIcenowy: btw: shouldn't you be in bed, for the "big day" tomorrow ? ;-)
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<MoeIcenowy>
too exciting to sleep ;-)
<MoeIcenowy>
and being worried to be not able to catch the bus ;-)
<MoeIcenowy>
oh it's now the time to book the bus ticket ;-)
<MoeIcenowy>
P.S. ANX980x is quite different from the two analogix drivers supported in mainline kernel now...
<MoeIcenowy>
(one is ANX78xx, the other is some embedded Analogix design in RockChip/Exynos SoCs
<jernej>
MoeIcenowy: Did you take a good look in jfm DRM driver for magic values? If I'm not mistaken, one of them is really a magic value, but others have explanation
<MoeIcenowy>
thx ;-)
<jernej>
MoeIcenowy: But I guess you don't have time for debating :)
<jernej>
MoeIcenowy: Good luck with the meeting
<MoeIcenowy>
I'm still considering what to talk at first ;-)
<MoeIcenowy>
GPL compliance issues should be put at some later position
<MoeIcenowy>
P.S. I think after a TCON1-only driver is ready the H3 TVE support can be made -- but I have still no way to connect a OPi Zero to my CVBS2USB card...
<jernej>
MoeIcenowy: I'm not sure about that, because CSC part of DE2 doesn't have GPL compliant source and I had to peek to that code to make it work...
<MoeIcenowy>
P.S. we can just make them magic numbers, like the ones in sun4i_backend.c
<jernej>
so I really hope you manage to convince Allwinner to put some GPL headers there
<MoeIcenowy>
and we can extract the magic numbers from a register dump ;-)
<jernej>
MoeIcenowy: I hate magic numbers and for most we know explanation, at least in DE2
<MoeIcenowy>
for rgb2yuv coeffecients it's difficult to explain...
<MoeIcenowy>
maybe some magic numbers declared in sun4i_backend.c can be reused?
<jernej>
MoeIcenowy: Anyway, now that I will really start to work on U-Boot HDMI DM driver, I could try in parallel start work also on kernel side
<jernej>
also for TV
<jernej>
I will check those numbers
<MoeIcenowy>
P.S. are there many differents between TVE in sun7i- and TVE in H3?
<jernej>
afaik, none, except clocks
<jernej>
U-Boot code is identical
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<jernej>
oh, yesterday I fixed TV out on H5
<jernej>
while H3 doesn't need calibration, H5 does
<jernej>
but fortunatelly, default, fixed number works
<MoeIcenowy>
jernej: can you try to replace the coefs in U-Boot DE2 driver with the coefs in sun4i_backends?