Turl changed the topic of #linux-sunxi to: Allwinner/sunxi /development discussion - did you try looking at our wiki? https://linux-sunxi.org - Don't ask to ask. Just ask and wait! - https://github.com/linux-sunxi/ - Logs at http://irclog.whitequark.org/linux-sunxi
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<wens> MoeIcenowy: thanks! i hate these little details
<wens> i'm still going to wait until all the existing dram patches hit u-boot-sunxi before sending any more though
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<wens> MoeIcenowy: i'm guessing the dram detection code still needs some work to support all kinds of combinations though
<wens> the original code can detect single/dual rank and full/half dq width
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<MoeIcenowy> wens: in fact we do not really support dual rank...
<MoeIcenowy> and today I will try to make mainline Linux support for R40
<wens> hmm, i already worked through r40 pinctrl once though
<wens> also have the basic dts files ready
<MoeIcenowy> I did my work with pinctrl variants
<MoeIcenowy> wens: have you made clk-ng?
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<wens> not yet
<wens> also haven't wrote code for pinctrl, only looked at differences
<MoeIcenowy> only differences @ PC?
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<wens> MoeIcenowy: maybe i push the dts files somewhere for you?
<MoeIcenowy> thx ;-)
<MoeIcenowy> or are there any other differences?
<MoeIcenowy> (I mean pinctrl
<wens> don't remember clearly, iirc there were some new pin functions, and a couple extra pins
<wens> nothing missing though
<MoeIcenowy> oh develop a clk-ng driver without user manual is a disaster
<wens> yup
<wens> you have to read the bsp
<wens> i planned to do that next, once i get all the stuff i had been doing finished
<wens> btw, i don't see sata in the bsp dtsi file
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<wens> bah, i looked at the wrong file
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<wens> MoeIcenowy: do you have pinctrl patches somewhere?
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<MoeIcenowy> wens: nope... I only did it yesterday
<MoeIcenowy> oh it's today in UTC+8 ;-)
<MoeIcenowy> P.S. the pll-periph{0,1} on R40 seems to have M factor...
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<wens> right, sun8i-r40 branch pushed to my github
<MoeIcenowy> wens: do you currently have the stock imge of R40
<MoeIcenowy> ?
<MoeIcenowy> so basic your DTSI is ;-)
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<wens> stock image? no
<MoeIcenowy> oh...
<MoeIcenowy> I wonder if the value of PLL6 register changes
<wens> you only add stuff that is supported and tested, so of course its basic
<wens> since almost everything depends on clocks
<wens> changes?
<MoeIcenowy> yes, for R40 the PLL6 seems to be a NKM clock
<MoeIcenowy> SUNXI_CLK_FACTORS(pll_periph0, 8, 5, 4, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 31, 0, 0, 0, 0); in stock
<MoeIcenowy> in contrast, SUNXI_CLK_FACTORS( pll_periph0, 8, 5, 4, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 31, 0, 0, 0, 0); for A64
<wens> so? then add it as nkm clock
<MoeIcenowy> I wonder whether the /2 fixed postdiv still exists
<MoeIcenowy> and the default value in U-Boot may also need to change
<MoeIcenowy> (we directly write 0x90041811 into pll6 cfg register now in U-Boot
<wens> why not just check the table of frequencies
<wens> looks like no post divider
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<MoeIcenowy> yes it seems
<wens> says it does :/
<MoeIcenowy> but I think the code may be wrong...
<MoeIcenowy> it's still 24*N*K/2
<MoeIcenowy> not 24*N*K/M
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<cini> noblock,I get uboot from github.com/apritzel/uboot sunxi64-beta but I cannt get sun50i_h5_spl32_defconfi. so ,should I get uboot from https://github.com/ehoutsma/u-boot.git?
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<MoeIcenowy> mripard: at least for V3s and R40 I found it necessary to have a parent reset line for a reset line...
<wens> which one?
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<MoeIcenowy> for V3s RST_USB_PHY depends on RST_USB_OTG
<MoeIcenowy> for R40's tcon, tvd, tve there's "*-top" reset lines which is depended on by seperate bus rsts
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<MoeIcenowy> or there's another solution -- pass both resets (the -top one and the seperate one) into the driver, and the driver deasserts the -top one in shared mode, and deassert the seperate one in non-shared mode
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<wens> is *-top in a separate address space?
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<cini> apritzel, noblock, my orangepi-pc2 can boot lasted linux with sdcard. cool, thanks. all works well with https://github.com/ehoutsma/u-boot-h5
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<wens> drm cleanup patches are stacking up
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<plaes> oh sweet
<wens> plaes: i haven't gotten to multiple pipeline support yet
<wens> fixing a bunch of stuff along the way
<plaes> yeah, that's always nice :)
<plaes> I'll probably have more free time in evenings from next month...:)
<oliv3r> tkaiser: toggeling PH3 and PH6 works fine and is somewhat exactly what i want
<oliv3r> tkaiser: but i want to do it from user space
<oliv3r> tkaiser: in a somewhat official/generic way
<oliv3r> by toggeling the USB vbus pins manually, i have to thus unbind them from the driver, meaning the driver no longer has control over the vbus
<plaes> extend rfkill to usb
<oliv3r> plaes: yeah that's one way of doing it
<oliv3r> plaes: but isn't rfkill only for radio devices?
<oliv3r> if i have a camera on usb1, is it appropiate to use rfkill for that?
<oliv3r> and how does rfkill work with usb right now? (i know it works for certain internal USB bluetooth adapters
<plaes> haven't investigated that :(
<oliv3r> i wonder what rfkill really does. tell the device to disable power
<oliv3r> or actually power off a port
<oliv3r> (if it can)
<wens> rfkill is just the framework
<wens> drivers might register an rfkill device with it, and the callbacks would toggle low power states
<oliv3r> well rf stands for Radio Frequency, so is it a bad name that was left behind?
<oliv3r> ah see, low-power state, i want to completly cut off power
<wens> don't think that works, since if you cut off power, the device disappears, and the rfkill device along with it
<oliv3r> i would expect a hard block to (in our case) cut off vbus entirely
<wens> rfkill only kills the rf part, hence the name
<oliv3r> ah see, so rfkill is not the proper solution :(
<wens> nope
<oliv3r> but toggeling ph3 maually via sys_gpio is very ugly too
<wens> though vendors do abuse it
<oliv3r> ideally, i want a user-space hook for phy_power_off
<wens> is it usb or sdio based?
<oliv3r> right now i'm trying to see if i can unbind ehci-platform (and ohci-platform) which does kill the power
<oliv3r> i want to cut power of the USB ports
<wens> that sounds like an idea
<oliv3r> yeah but right now, when i re-enable power, the atheros driver crashes :
<wens> :/
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<oliv3r> so i may have to unbind the ehci-platform driver, unload the usb drivers (ath9k/uvc) etc
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<oliv3r> (or unbind ath9k in more then one spot)
<oliv3r> anyhow, rfkill is not tied into the phy_power_off in any way
<oliv3r> it seems only the platform drivers are
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<MoeIcenowy> wens: no, *-top is directly after seperate gates/resets
<wens> hmm
<wens> on the a80 they were in different address spaces, so i just did a separate device driver for them
<MoeIcenowy> https://pastebin.anthonos.org/view/e2c1d79a here's a list of R40 gates & resets by introspecting BSP clock driver
<wens> what about usb clocks?
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<MoeIcenowy> wens: you mean usb clks/rsts @ 0xcc?
<wens> MoeIcenowy: yup
<MoeIcenowy> wens, mripard: I have a question: if a clock have two parents configurable, one is only used by this clock as parent, and the other is a common parent, can I set the clock as CLK_SET_RATE_PARENT
<MoeIcenowy> (or specified: the sata mod clk on R40 have two parents: pll-sata and pll-periph0
<MoeIcenowy> (and it's a mux only clock
<MoeIcenowy> wens: I didn't record 0xcc clocks to the doc, as I directly modified the ccu-sun8i-r40.c
<wens> the sata clock probably will never change
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<MoeIcenowy> but if there's no CLK_SET_RATE_PARENT I think it won't change pll-sata
<wens> but to be safe you can do CLK_SET_RATE_PARENT + CLK_NO_REPARENT, and force the parent to pll-sata
<MoeIcenowy> how to force parent?
<MoeIcenowy> should force parent in dt?
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<MoeIcenowy> OOPS! THE BSP CLOCK CODE OF R40 SHOWS A COLLISION ON DRAM_GATE 2!
<MoeIcenowy> both deinterlace and csi1 uses DRAM_GATE 2
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<wens> MoeIcenowy: call clk_set_parent in the ccu probe function :)
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<Wizzup> I have an Olimex A64 board, is anyone working on any dtses/u-boot patches?
<plaes> which board?
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<plaes> Wizzup: if you have the board, then please start contributing to the wiki
<swabbles> problem is, we currently lack a working u-boot/Linux kernel.
<swabbles> sunxi-fel does work though.
<plaes> well, Olimex also is not yet selling A64 boards
<Wizzup> this is a sample
<Wizzup> I can make pictures and add to the wiki
<Wizzup> I will mail them about a repo for u-boot/kernel
<plaes> ok, please do
<Wizzup> in the evening I will
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<jelle> I think I'll wait on the orange pi pc2 merge before I start on the nanopi a64 :P
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<jernej> MoeIcenowy: I found issue for DE2 on A64!
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<jernej> MoeIcenowy: 24 bit in some syscon register (0x01c00004) must be cleared
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<jernej> MoeIcenowy: BSP explanation of register is: "set sram for vedio use, default is boot use"
<jernej> actually, explanation of clearing that bit
<jernej> apritzel: do you know anything of above register? Should I make a patch for mainline U-Boot? Allwinner cleared this bit in board_init() function
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<CuteIcenowy> jernej: THANKS!
<CuteIcenowy> jernej: as it's only DE-related, clear it in sunxi_composer_init it enough
<jernej> well, in the end, it was just one bit
<CuteIcenowy> magic bit ;-)
<CuteIcenowy> I discovered many magic bits since I started mainline sunxi development ;-)
<CuteIcenowy> and maybe we can find it more easily if they didn't have the typo of vedio ;-)
<jernej> do you know what "vedio" means?
<jernej> ah, video :)
<CuteIcenowy> It's the kind of allwinner typo ;-)
<CuteIcenowy> like "eraly jump fel" ;-)
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<CuteIcenowy> (eraly jump fel is a log text in boot0
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<MoeIcenowy> ok my ZNC is back ;-)
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<MoeIcenowy> my ccu-sun8i-r40 passed compilation ;-)
<jernej> MoeIcenowy: Now, instead of asking for DE2 issue, you could ask for full A64 syscon description :)
<MoeIcenowy> oh it's Feb 17 now
<jernej> still 16 for me :)
<MoeIcenowy> I haven't closed the problems page
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<MoeIcenowy> P.S. I remembered when I made sunxi-cedrus work on A33
<MoeIcenowy> it's also a syscon magic bit ;-)
<jernej> so syscon description would be very useful
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<MoeIcenowy> in former SoCs (A33-) there's syscon description
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<jernej> MoeIcenowy: regarding mixer/tcon selection discussion
<MoeIcenowy> ?
<jernej> yesterday
<jernej> for mainline kernel driver
<MoeIcenowy> yes...
<jernej> I think BSP kernel always use mixer0 of there is only one output enabled, which is usually most of the time
<MoeIcenowy> P.S. I think for R40 there will be a bigger disaster
<jernej> so I guess it makes most sense to always use mixer0 if only one output is enabled and maybe default relation if both are enabled
<MoeIcenowy> R40 have 4 TCONs...
<jernej> really?
<jernej> do you have datasheet?
<MoeIcenowy> tcon0, tcon1, tcon-tve0, tcon-tve1
<MoeIcenowy> I checked ccu-sun8iw11.c
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<MoeIcenowy> (I also asked some BPi guy for the datasheet
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<MoeIcenowy> r40 have 4 tcons, 2 tves, 4 tvds
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<apritzel> swabbles: Wizzup: checkout the Pine64 Wiki page, I updated kernel and U-Boot part lately
<apritzel> for U-Boot, use my sunxi64-beta branch from my github for now
<apritzel> chances are that pretending to be a Pine64 gets you pretty far
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<apritzel> Wizzup: "I will mail them about a repo for u-boot/kernel"> for what purpose?
<apritzel> Wizzup: to get some code from them?
<Wizzup> apritzel: I was assuming the u-boot from pine64 will not work on olinuxino a64 per se?
<apritzel> Wizzup: I take it this a bog standard A64 board, so just copy&pasting some existing (upstream) A64 board DT should make this work for you
<apritzel> Wizzup: why not?
<Wizzup> apritzel: Cool, that is what I would like to do/try.
<Wizzup> n.b. swabbles said he got the orange pi zero u-boot spi driver to work (H2)
<apritzel> Wizzup: actually just taking a literal Pine64 setup should get you going already
<Wizzup> I will try it tonight, tomorrow, or at latest, in the weekend. I planned to make some photos now and make a wiki page.
<jemk> apritzel: i've cleaned up my toc0 generation script: https://gist.github.com/jemk/2abcab1359c4bce793679c5854062331
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<jemk> i wont do any more secure boot stuff in near future, but if you have some questions i'll see if i can answer them
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<apritzel> jemk: Oh, awesome! I had integration into mksunxiboot.c on my plan, but seems like I can skip this ...
<apritzel> jemk: thanks and no worries, I can take it from here
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<jemk> apritzel: mksunxiboot would be nice, but i didn't want to fight with openssl in c
<apritzel> jemk: so this did work for you on an H3 board?
<jemk> yes, so far no issues, but i didn't program a rotpk yet
<apritzel> jemk: hehe, I C, don't plan to do this anytime soon either ...
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<apritzel> jemk: are those "efuses" real fuses, so only OTP?
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<jemk> it should work, and even if it fails it should be possible to fix this via fel by programming it to all 1 (should be possible with efuse)
<apritzel> so you can turn each bit once from 0 to 1, and that's it?
<jemk> thats how i know efuses, but i don't know if thats how sunxi-ones work
<apritzel> normally it's the other way 'round, right? From 1 to 0 ...
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<jemk> hm, possible, maybe i'll just try it some day, fel wont break
<apritzel> anyway, thanks a ton, that should solve a long standing issue for me (missing TZ security on the A64)
<MoeIcenowy> apritzel: out-of-tree build is broken on your sunxi64-beta
<apritzel> MoeIcenowy: out-of-tree build?
<MoeIcenowy> make -C ../u-boot O=$PWD ...
<apritzel> MoeIcenowy: ah, I see
<MoeIcenowy> as I only keep one source tree for many builds
<MoeIcenowy> I deeply depends on out-of-tree build
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<apritzel> yeah, that's nasty, have to see if I can find some magic in the generator script to work around this
<apritzel> MoeIcenowy: I guess this is where it fails, right?
<apritzel> to find the DTBs and/or ATF
<Wizzup> apritzel: btw, I think that you don't need to use 'sync' if you use dd (from your readme in the pine64 repo)
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<apritzel> Wizzup: well, it's "sync" on the shell or conv="fsync", I guess
<Wizzup> I thought sync only operated on the cache, and I don't think io on block devices goes through that cache?
* Wizzup googles
<Wizzup> Apparently you're right. TIL
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<apritzel> Wizzup: if you do larger dd transfers to a slow SD card, you actually *see* that it's much faster than it should be ;-)
<apritzel> so dd may finish quickly, then "sync" blocks for quite a while
<Wizzup> I was under the impression that only mattered on filesystems, e.g. when VFS is used
<Wizzup> But apparently not
<dgp> That would mean that the cache would need to know how each and every FS works
<MoeIcenowy> apritzel: it seems that opi pc2 support if also broken
<Wizzup> dgp: Isn't that why we have the VFS?
<MoeIcenowy> s/if/is/g
<apritzel> MoeIcenowy: how?
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<MoeIcenowy> dtc: option requires an argument -- 'E'
<apritzel> MoeIcenowy: I didn't enable the FIT magic for it, if that is what you mean
<dgp> Wizzup: But if you do it in the VFS you don't get caching for LVM etc
<MoeIcenowy> but the magic try to make effect.
<apritzel> MoeIcenowy: ah, because of the uboot.itb target being defined for arm64
<apritzel> MoeIcenowy: thanks, will fix it later
<apritzel> MoeIcenowy: I actually just put the H5 patches up front because I was expecting them to be merged earlier than the others
<apritzel> and there are some minor conflicts if you swap the order
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<MoeIcenowy> wens: didn't you implement PSCI for R40?
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<jelle> does anyone know how to deal with emmc?
<jelle> I have Disk /dev/mmcblk2: 7.3 GiB, 7818182656 bytes, 15269888 sectors
<jelle> now on my nanopi neo? I can just format that etc.
<beeble> yes?
<beeble> think of it as a onboard sd card
<jelle> beeble: ah
<beeble> use it in the same way
<beeble> what cpu?
<jelle> beeble: h3
<beeble> not sure how the bootorder is on h3, don't have one
<beeble> so depending on brom it will probe the emmc for e.GON header
<beeble> if it's like the A64 it will be the second after the sd card
<beeble> on other cpus it will be the second after spi0
<jelle> beeble: no h3 there
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<beeble> but there are no bootsel pins on h3 as on the a64. so it will probe all the interface in some order
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<beeble> as long as there are no fuses set
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<jelle> hmm some order
<beeble> take the sd card out if you want to be sure to boot from emmc :)
<jelle> ah ok
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<beeble> same 8k offset
<beeble> to but the spl
<beeble> put
<jelle> thanks
<beeble> ah and with mainline dts the mmcblk will be reorderd depending on if there is a sd card plugged in or not
<beeble> so keep that in mind for bootargs
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<jelle> beeble: thanks, going to try bluetooth first
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<beeble> apritzel: do you have already a uboot/atf branch where you can send axp requests for read/write?
<beeble> apritzel: interactive, if not no problem. i will implement it myself. just don't want to do duplicated work
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<beeble> apritzel: nvm. was less wirk then i thougt
<apritzel> beeble: what for, exactly?
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<apritzel> I have some SCPI framework in ATF, which can be easily connected to a SCPI regulator or power domain
<beeble> apritzel: have to debug IPS from second stage uboot. so i have to read and write random registers. but found how to implement that with scpi and services/std_svc/std_svc_setup.c
<beeble> that can be done easily with what you already provide
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<apritzel> beeble: well, if it's just for debugging: I used my peekpoke tool from Linux for that, using RSB is easy with just a simple sequence of MMIO commands
<beeble> apritzel: i now have smc axp reg. since my teating results in a lot of reboots i prefer to do it in uboot to reduce turnaround times
<BenG83_PB> I will probably do something similar...
<BenG83_PB> Pinebook charges really slow sometimes
<apritzel> beeble: I think there is some stub rsb command in U-Boot already
<BenG83_PB> need to play a bit with register settings
<apritzel> if not then I quickly hacked, can't remember anymore ;-)
<beeble> apritzel: i'm already finished :)
<MoeIcenowy> wens: I have already locally get R40's MMC to work ;-)
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<willmore> BenG83_PB, is the power setup on the PineBook anything like the Pine64 with a battery attached?
<BenG83_PB> PB has a 10Ah LiPo
<BenG83_PB> but as always, no one changed the battery parameters in the dts
<BenG83_PB> just trying to tweak things a bit
<BenG83_PB> aside from the sizes, battery setup is the same
<BenG83_PB> trying to figure out how I can dynamically adjust the charge current
<BenG83_PB> instead of the fixed limit
<willmore> BenG83_PB, wonderful. I hope you're documenting what you learn. :)
<BenG83_PB> well I am mostly a hardware guy so I know what I want to do
<BenG83_PB> just not how to integrate this with Linux
<BenG83_PB> and the different parts like the ATF, AR100 etc
<apritzel> the question is why Linux should be involved in it in the first place?
<willmore> It's a pretty deep rabbit hole. ;)
<BenG83_PB> it would be much easier if I could just talk to the AXP directly
<BenG83_PB> I want to charge the battery with 3A if the PB is off
<BenG83_PB> and adapt charge current to load if the PB is on
<BenG83_PB> atm is just has a fixed limit of 1200mA
<BenG83_PB> since that is the AXP default
<apritzel> so why would you want to do it in Linux?
<BenG83_PB> under load, the battery almost discharges
<willmore> There's no way to tell the AXP that the input current has a limit and let it do the work?
<apritzel> I consider this a firmware things
<apritzel> in the end this is what real laptops (TM) do
<BenG83_PB> if it can be done in ATF I am good with that
<BenG83_PB> there are limit for BAT, DC, USB rails
<willmore> It's generally easier to debug processes in a full OS and then later commit them to firmware.
<BenG83_PB> and some budgeting functions
<apritzel> whether it's ATF or the arisc is actually an implementation detail
<BenG83_PB> the way mainline will do it is without arisc, right?
<apritzel> I don't know how we will do this
<apritzel> so far we don't have anything on the arisc
<apritzel> because we don't need anything there
<apritzel> and it's just additional churn
<apritzel> if battery charging requires constant hand holding, that looks like a task for the arisc
<BenG83_PB> I would start with making a model
<BenG83_PB> how charging should work in different states
<BenG83_PB> and then see how to implement it with what the AXP can do
<BenG83_PB> based on a power input budget
<BenG83_PB> and some state info from the OS
<willmore> BenG83_PB, what's the power supply on the PB?
<BenG83_PB> there is a hard input limit of 3A
<willmore> Due to?
<BenG83_PB> input regulator
<BenG83_PB> has programmable cut off
<BenG83_PB> according to the schematic
<BenG83_PB> its set to 3A
<BenG83_PB> the AXP can do 4A max iirc
<willmore> Let me try again. What is the physical supply of power for the PB and how does it mechanically connect to the PB?
<willmore> Some kind of power brick? With a barrel connector?
<BenG83_PB> barrel connector
<willmore> Okay, so there is no signaling with the power supply a la USB-PD.
<BenG83_PB> no
<willmore> So you're designing this assuming a power supply that can handle the full limit of your power input circuitry which is 3A?
<BenG83_PB> yes
* willmore is just trying not to make assumptions
<BenG83_PB> I think they went a bit on the low side with 3A
<willmore> Agreed. If you put a 10Ah pack in it, 3A is quite low.
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<BenG83_PB> if I consider what I know from my Pine boards
<willmore> Is it just a 1S lithium pack?
<BenG83_PB> plus the LCD and backlight
<BenG83_PB> the battery is 1S2P
<BenG83_PB> 10Ah
<willmore> So, two 5A Li-po slabs?
<BenG83_PB> yes
<willmore> Yeah, 3A is tiny.
<BenG83_PB> i was thinking about adding some custom charging circuirty ;)
<willmore> But, if the power handler chip can only do 4A, it's not that much worse.
<BenG83_PB> yeah
<willmore> Are you with Olimex?
<BenG83_PB> no just a Pine user
<willmore> Okay.
<BenG83_PB> i got a PB prototype during FOSDEM from Tl
<willmore> Wonderbar.
<BenG83_PB> currently trying to get some Linux running
<BenG83_PB> and fixing some laptop related things
<willmore> You're got your work cut out for you.
<BenG83_PB> I think it would already help if one would set the full charge current in the AXP on shutdown
<BenG83_PB> so it doesnt take like 10h to charge the battery
<willmore> I would have hoped that you could just tell the AXP the input power limit and the battery power limit and just walk away and let it do what needs done.
<beeble> it's not a lot more than that
<BenG83_PB> I think it can reduce battery charge current if the PS rail needs to much power
<beeble> just a bit to decicde the running state and deciding on the ACIN available bit
<BenG83_PB> need to read the AXP datasheet again
<beeble> there should pretty much everything already available in ATF and SCPI enabled mainline
<beeble> with 3.10 bsp you would have the arisc inbetween
<BenG83_PB> we spent a lot of time at work designing power managment around MCUs (mostly CortexM) for mobile devices, so I have some experience on the hardware side
<BenG83_PB> we usually dont do much with Linux based embedded systems so I learn a lot atm ;)
<BenG83_PB> yeah I am using longsleeps 3.10 BSP kernel atm
<BenG83_PB> mostly because I need a display driver to use the PB
<apritzel> beeble: yeah, the Allwinner design is really convoluted, and I fail to see the reason for that: Linux calls ATF via an smc call, which in turn uses the mailbox to communicate with the arisc, which then writes the value into the AXP
<apritzel> I would understand that if there would be some kind of abstraction, but it's really AXP address and value pairs passed on
<BenG83_PB> can the arisc access periperals?
<apritzel> yes
<apritzel> except the GIC (the ARM interrupt controller)
<apritzel> which is an architectural limitation
<BenG83_PB> so you could do all sorts of interesting things in a ultra low power state...
<apritzel> yes
<apritzel> that's the idea, I guess
<apritzel> you could even snoop the Ethernet or Wifi
<beeble> apritzel: the only thing i can think of is that you can still use the arisc stand alone without any of the arm cores running. and just using the atf because you expect them to have it on arm :)
<beeble> *arm64
<apritzel> beeble: yes, I am afraid so as well ;-)
<apritzel> it would be much smarter to just call from Linux into the arisc with the mailbox, and then use some kind of abstracting, probably standardised protocol
<apritzel> yes, SCPI is not perfect, but it's the only standardised interface for that purpose I know of
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<lurchi_> Is anyone working on audio support for the Pine64/A64?
<apritzel> lurchi_: I think I saw some success reports already here in the last few days
<apritzel> lurchi_: check the wiki
<lurchi_> apritzel: According to the matrix, H3 is supported currently, A64 is not
<apritzel> though that might be I2S only, atm
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<lurchi_> apritzel: thanks, seems to be I2S and SPDIF
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<apritzel> jemk: does your Ruby actually have a .sum method on arrays?
<apritzel> mine at least doesn't, so with some little help from Dr. Google I replaced it with ".inject(:+)"
<apritzel> I see some issue with the SPL size, I guess we need to reserve some space for the TOC0 header?
<apritzel> your script creates a 48KB file, I guess because of alignment
<apritzel> also for A64 the load address is 0x10000
<apritzel> but long story short: at least it accepted the SPL on an SD card on my "secure" Pine64!
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<apritzel> jemk: and yes: cutting 800 Bytes off the SPL before giving it to mktoc0 makes it go even further and execute ATF!
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