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<
Dodger78_ >
should spdif be working in mainline kernels now ? or is a dts update missing ?
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<
plaes >
Dodger78_: IIRC it's not yet merged
12:51
<
plaes >
or.. if it is it will be in 4.7
12:52
<
Dodger78_ >
@pleas , the SPDIF modu sup is already in latest head
12:53
<
codekipper >
Dodger78_: I'll try to push the rest of the patches this weekend.
12:54
<
codekipper >
which board do you have?
12:54
<
Dodger78_ >
cool thank you !!
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<
tkaiser >
longsleep: (or any other Arch Linux user). I just booted the Pine64+ with your Arch image, had a look around and finished a monitoring template.
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<
swiftgeek >
A10/13 are using VIC right?
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<
ddc >
hi everyone I'm working on the su4i csi and I made a good progress but I'm having strange issue with clock it works fine if I boot from mmc but not from the nand
16:41
<
ddc >
Not sure if it is something to do with DMA
16:42
<
ddc >
Any help will be appreciated
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<
gusenkovs_ >
Kernel : Linux 4.2 Mainline 204.899412] fb_ili9486 spi32766.0: SPI transfer failed: -22 [ 204.905048] spi_master spi32766: failed to transfer one message from queue [ 204.905093] fb_ili9486 spi32766.0: fbtft_update_display: write_vmem failed to update display buffer
16:46
<
ddc >
I do deassert the clock in the driver
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<
ssvb >
tkaiser: "sysbench --test=cpu --cpu-max-prime=400000 run --num-threads=4" is pretty weak on Pine64, it only adds something like 200mA current draw at 1GHz
16:53
<
ssvb >
a multithreaded litecoin miner adds ~700mA current draw in the same conditions
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<
tkaiser >
ssvb: How long does a test with --cpu-max-prime=20000 take with your config?
16:56
<
ssvb >
tkaiser: 9 seconds
16:57
<
tkaiser >
ssvb: Here as well
16:57
<
ssvb >
btw, a multithreaded variant of cpuburn-a8 adds ~650mA current draw (a bit weaker than the litecoin miner)
16:58
<
tkaiser >
Will try that next
16:59
<
ssvb >
cpuburn-a8 is more efficient than cpuburn-a7 and cpuburn-a9 on Pine64, but I will probably make a cortex-a53 tuned version soon
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<
tkaiser >
ssvb: Could you provide a binary? Not able to compile
17:00
<
tkaiser >
Of the a8 version?
17:00
<
ssvb >
tkaiser: you need to compile a 32-bit static binary of cpuburn-a8 if you want to try it
17:01
<
ssvb >
just run "arm-linux-gnueabihf-gcc -static -o cpuburn-a8 cpubuen-a8.S"
17:01
<
ssvb >
and then run multiple instances of it
17:04
<
tkaiser >
Thx, already testing
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<
tkaiser >
Nice, already 101¡C
17:08
<
tkaiser >
ssvb: I stopped at 105¡C internal read out. The SoC was also really hot (ouch). And the 3.10.65 kernel reduced cpufreq already down to 816MHz
17:09
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17:09
<
tkaiser >
Also ~600mA more
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<
tkaiser >
ssvb: How is VDD_CPUX set?
17:16
<
tkaiser >
So 1008 MHz @ 1.1V?
17:16
<
ssvb >
tkaiser: now we have the Pine64 schematics and can get a more detailed information from it (haven't looked at it yet)
17:17
<
ssvb >
more likely 1008 MHz @ 1.2V according to the dvfs table
17:17
<
tkaiser >
Yes, in my case. And at 816MHz it's switching to 1.1V
17:18
<
tkaiser >
With the 3.10.65 kernel this is available as /sys/devices/platform/axp81x_board/axp-regulator.41/regulator/regulator.2/microvolts
17:20
<
apritzel >
CPUX is driven by the dual phase DCDC 2 & 3 and defaults to 1.1 V
17:21
<
tkaiser >
apritzel: That was my question before. Mainline is using 1008MHz with 1.1V then?
17:21
<
tkaiser >
Or do you already have dvfs working?
17:21
<
apritzel >
that depends on what firmware you are running
17:21
<
apritzel >
with Allwinner's U-Boot: yes
17:21
<
apritzel >
I think ssvb clocked the CPUs down
17:22
<
apritzel >
(in his U-Boot port)
17:22
<
apritzel >
for now Linux does not touch either the voltage or the clock
17:22
<
apritzel >
(mainline Linux, that is)
17:22
<
tkaiser >
Thank you both
17:23
<
apritzel >
I am just about to enable the AXP803 in U-Boot
17:23
<
apritzel >
struggeling with the RSB, though
17:23
<
apritzel >
I get an transfer error after initialization
17:24
<
apritzel >
I guess there I have either the wrong reset bit or the clock is still gated
17:24
<
apritzel >
cannot find anything in the A64 manual
17:24
<
apritzel >
about the RSB
17:24
<
apritzel >
and the RSB init is done in the arisc code, which we don't have, AFAIK
17:25
<
apritzel >
I will try to look in the BSP kernel anyway, they had #ifdef'ed section for running without the arisc, IIRC
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<
wens >
apritzel1: hoping the RSB controller didn't change
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<
apritzel >
wens: me too ;-)
18:50
<
apritzel >
the kernel tree in the BSP was a dead end
18:50
<
apritzel >
they use the arisc to wrap this
18:50
<
apritzel >
but in their U-Boot there is some RSB code
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