Turl changed the topic of #linux-sunxi to: Allwinner/sunxi /development discussion - did you try looking at our wiki? https://linux-sunxi.org - Don't ask to ask. Just ask and wait! - https://github.com/linux-sunxi/ - Logs at http://irclog.whitequark.org/linux-sunxi
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<wens> MoeIcenowy: I have no idea
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<montjoie> raaah still perf/4 for sun8i-ce (vs aes-generic)
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<MoeIcenowy> wens: I changed all GIC accesses to the aliased one, and now the system doesn't hang but say "CPUx: failed to come online"
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<MoeIcenowy> P.S. according to the BSP source code the mysterious sun8iw9 is a SoC with 6 CPU cores: 2 clusters, 3 cores per cluste
<MoeIcenowy> cluster
<terra854> Did it say anything about what core does it have?
<MoeIcenowy> A7, of course ;-)
<MoeIcenowy> OK got quad core to run on A83T
<MoeIcenowy> wens: I'm now sure that the GIC problem not only exists on A83T, but also can totally block the PSCI to be used if not workarounded
<wens> yeah, exactly like the A80
<MoeIcenowy> let me make a GIC property for it
<MoeIcenowy> allwinner,secure-broken; ?
<terra854> 2 clusters of 3x A7?
<terra854> I was thinking like a cluster of A15 and a cluster of A7
<terra854> in a big.LITTLE configuration
<MoeIcenowy> that SoCs will be called sun9i instead of sun8i .
<MoeIcenowy> As it's named sun8iwx, it surely contains only A7
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<MoeIcenowy> wens: or should I make a more compatible for it? allwinner,sun9i-a80-gic ?
<MoeIcenowy> I don't think it's a bug by ARM, but a bug by Allwinner...
<MoeIcenowy> so maybe it will be better to call it allwinner,always-secure
<wens> the vendor for the GIC is ARM
<terra854> Did anyone have an A80 device?
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<MoeIcenowy> terra854: wens ;-)
<terra854> And did anyone got ahold of a H8vr device?
<MoeIcenowy> me
<terra854> VR headset or SBC?
<MoeIcenowy> VR headset
<MoeIcenowy> H8vr should be just H8 -- it returns "A83T" in FEL
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<terra854> I think that A83T and H8vr are one and the same...
<MoeIcenowy> yes
<MoeIcenowy> and H8
<olerem> hallo all, i provided devicetree patch for Banana Pi directly to mainline. This patch was Acked but avaiting for sunxi maintiner https://patchwork.kernel.org/patch/9264879/
<olerem> who is the right person to contact?
<KotCzarny> you have one in CC:, wens
<olerem> ok, thanks
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<KotCzarny> his nick is the same her, just fyi
<KotCzarny> *here
<olerem> wens: ping
<wens> olerem: pong?
<olerem> wens: hi, this patch needs you https://patchwork.kernel.org/patch/9264879/
<wens> olerem: you have to send it to both maintainers
<MoeIcenowy> and for sunxi I think mostly Maxime Ripard merges the patches
<wens> olerem: I'm not the one picking up patches, though that will change beginning with the next cycle
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<olerem> oleksij@zwerg:~/tmp/linux$ ./scripts/get_maintainer.pl arch/arm/boot/dts/sun7i-a20-bananapi.dts | grep main
<olerem> Rob Herring <robh+dt@kernel.org> (maintainer:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS)
<olerem> Mark Rutland <mark.rutland@arm.com> (maintainer:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS)
<olerem> Russell King <linux@armlinux.org.uk> (maintainer:ARM PORT)
<olerem> Maxime Ripard <maxime.ripard@free-electrons.com> (maintainer:ARM/Allwinner sunXi SoC support)
<olerem> Chen-Yu Tsai <wens@csie.org> (maintainer:ARM/Allwinner sunXi SoC support)
<olerem> wens: both means?
<olerem> you and Maxime?
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<wens> olerem: yes
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<olerem> wens: ok. should i set your Acked-by?
<MoeIcenowy> wens: I will try to do octa-core on A83T now
<MoeIcenowy> as I'm based on your code I think it may be not so difficult to re-adapt it back to A80
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<MoeIcenowy> so strange... If I initialize CCI it will fail to boot...
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<wens> you have to bring up the cluster L2 caches before you enable CCI
<wens> otherwise it will hang waiting for transactions
<MoeIcenowy> I found it ;-)
<wens> if you want to be lazy, just initialize it before boot, like the original a83t psci series did
<wens> obviously the better way would be to initialize it when the cluster is brought up, and disable it if it is shut down
<MoeIcenowy> I think initialize it before boot is more proper ;-)
<MoeIcenowy> oh I found that sunxi_get_revision shouldn't be implemented as function, but should be a macro...
<wens> you can implement it as a function
<wens> you just have to make sure that __secure code only calls __secure code
<MoeIcenowy> thus I will need two copy of it
<wens> why 2?
<MoeIcenowy> (because I want to print the revision number during boot, as it really matters
<MoeIcenowy> (and it may furtherly be used more
<wens> ok
<MoeIcenowy> oh the A83T FEL load speed is so slooooooow...
<MoeIcenowy> wens: your workaround seems to have some problem -- if PSCI is not present it will lead to system panic
<MoeIcenowy> (GIC workaroud
<wens> yeah, i just fixed it
<wens> please wait
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<wens> oops, think I broke something again
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<wens> updated, though it still doesn't work well to unplug cores
<wens> it just hangs
<MoeIcenowy> oh the cluster 1 cpus do not want to start...
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<wens> MoeIcenowy: there is a reason I put that on hold
<MoeIcenowy> wens: ;-)
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<montjoie> how to change bus_ce clock to 300Mhz ? clk_set_rate() end with success but no change
<montjoie> does I need to reparent to pll-periph0 ?
<wens> you cannot change bus_* clock
<wens> do you mean ce clock?
<montjoie> in /sys/kernel/debug/clk/clk_summary it is bus-ce
<montjoie> ahb1_ce in DT
<wens> the bus clocks are not designed to be changed, as the bus is shared
<montjoie> the datasheet said CE clk could be up to 300, so I expect better performance
<wens> there is another "ce" clock
<wens> that is the module clock
<montjoie> yes the "mod" clock but it is already at max
<montjoie> 24Mhz
<wens> what?
<wens> how can that be
<wens> what platform are you working on
<montjoie> pine64
<wens> a64 manual 1.0, page 109/110
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<wens> the CE clock can definitely go above 24 MHz
<montjoie> oups wrongly read >=
<montjoie> so I could tyr 48Mhz ?
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<montjoie> but the parent is already at max 24Mhz
<wens> it can be muxed to pll-periph-2x
<wens> just set a higher rate, like 200 MHz, and it will switch over
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<BenG83> morning
<BenG83> codekipper, did tllim get in touch with you?
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<karak> Hi, to All! Please, tell me, how I can adjust of R_UART baud rate? I have output from R_UART on custom board based on A80. I see a garbage on linux terminal and try all of them (9600, 19200, ... 115200) with the same result.
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<KotCzarny> nice. libvdpau-sunxi is going to be updated soon, with fixed color space and stuff, already working great
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<oliv3r> wens: thanks for pointing out my oversight :)
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<BenG83> !seen ssvb
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<oliv3r> wens: my confusion probably came from the fact, that th eDW_UART_USR define is 8bit aligned, and immediatly following that define, we have the DW_UART_CPR and UCV defines, which are 32bit aligned.
<diego_r> Hi, is "Emmanuel Vadot" lurking in here? https://lists.denx.de/pipermail/u-boot/2016-June/258114.html
<montjoie> wens: what is the maximum safe value ?
<ElBarto> diego_r: yep
<diego_r> Hi ElBarto / Emmanuel. I'd like to get the above patch finished and upstreamed. Are you the original author of the patch? How do you want to be credited?
<ElBarto> diego_r: yes I'm the original author, I was sure that I did resend it or that someone else did ...
<montjoie> wens: very very little increase at 200Mhz
<diego_r> ElBarto: it's not there yet. http://git.denx.de/?p=u-boot.git;a=tree;f=configs
<ElBarto> diego_r: ok, well if you want to finish the work be my guest
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<MoeIcenowy> wens: 7 core succeeded
<MoeIcenowy> the cluster 1 core 0 has some different behavior on Rev.A and Rev.B on A83T so I will soon enable it
<oliv3r> i think i even sent a emmc defconfig for the lime2 at some point
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<oliv3r> maybe i'm confused
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<oliv3r> diego_r: are you going to resend it?
<oliv3r> otherwise i'll git send-email mine, as I have it locally committed already anyway
<diego_r> ElBarto: as you prefer. Do you want to me go on or do you prefer to finish what you started?
<oliv3r> i think it was not merged back then, as it needed some rework and the dts wasn't merged yet
<ElBarto> diego_r: check with oliv3r, if he have a patch that he's using maybe it's best if he send it
<ElBarto> oliv3r: dts was wrong on the emmc pins anyway
<ElBarto> I don't remember when I fixed that, maybe january ?
<oliv3r> ElBarto: is u-boot not usign the upstream dts; so the pins should be right no?
<diego_r> oliv3r: ElBarto: three guys for one tiny change are too many :) Let's just figure out who's ahead with this one and then decide.
<ElBarto> ah no it wasn't the pins
<oliv3r> ah the pwrseq bit
<BenG83> did BSD projects get Pinebook samples?
<wens> MoeIcenowy: seems max is 400 MHz, according to the manual
<oliv3r> yeah i actually removed it from my local set as it didn't work :)
<ElBarto> BenG83: we should received some soon I hope
<BenG83> ok
<BenG83> ping me if there are any issues
<wens> MoeIcenowy: that bit is stupid, why would they change that between revisions
<ElBarto> BenG83: and that's for FreeBSD, don't know about the others
<MoeIcenowy> wens: I don't lnow it
<MoeIcenowy> wens: are you replying montjoie with 400MHz?
<wens> MoeIcenowy: it was a rhetorical question...
<wens> MoeIcenowy: oops, yeah
<montjoie> :)
<montjoie> wens: sure that's impossible to put bus_clk to 300 ?
<wens> montjoie: maybe DMA can't keep up?
<wens> montjoie: you could do it in U-boot, but I recommend not touching the bus clocks once in Linux
<MoeIcenowy> In fact the only error that prevented me from getting cluster1 to work is wrongly setting the length of cpu_pwr_clamp array in PRCM
<ElBarto> oliv3r: will you take care of sending this defconfig ?
<MoeIcenowy> but I didn't cherry-pick your cpu_off commit now, only cpu_on is supported
<oliv3r> ElBarto: sure
<diego_r> ok. oliv3r, let me know if you need any helping hand
<MoeIcenowy> wens: but the newest user manual of A83T showed only the situation of Rev.B
<oliv3r> actually its kinda good your version wasn't merged back then, it still uses the old (and crashing) 480 Mhz
<MoeIcenowy> oh hooray "smp: Brought up 1 node, 8 CPUs"
<oliv3r> i will actually add it to my changeset that implements the AXP LDO3 fix
<oliv3r> hmm, maybe not; i'l send it first
<oliv3r> as i have to do some work on that sent
<MoeIcenowy> P.S. My chip is Rev.B, and I don't know who has a Rev.A
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<MoeIcenowy> wens: what's the CPUID number format of ((readl(GICC_BASE + GICC_IAR) >> 10) & 0x7) ?
<MoeIcenowy> is it in mpidr format (0x100 for cluster 1 core 0) or is it in dense format (0x4 for cluster 1 core 0)?
<wens> iirc dense
<wens> the GIC only has 8 interfaces, and they are numbered 0~7
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<MoeIcenowy> ok CPU hotplugging doesn't work well here on A83T
<MoeIcenowy> even in cluster 0
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<oliv3r> diego_r: done
<MoeIcenowy> wens: you can enable BPi M3 usb_otg in peripheral-only mode now in your branch
<MoeIcenowy> that is useful
<diego_r> oliv3r: seen the email. Nice, thanks
<MoeIcenowy> rather than leave them disabled
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<wens> MoeIcenowy: I had a patch doing that
<wens> or was it for host mode
<MoeIcenowy> you only enabled h8homlet evb as host mode
<MoeIcenowy> and the other 2 boards (bpi-m3 and ct+) have usb_otg left disabled
<wens> not really a priority for me now though
<parazyd> load mmc 0:1 0x43000000 ${fdtfile} || load mmc 0:1 0x43000000 boot/${fdtfile}
<parazyd> the ${fdtfile} here is a path, right? so it can be also: dtbs/${fdtfile} ?
<wens> yes
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<MoeIcenowy> wens: could you look at my a83t psci code?
<parazyd> wens: thx
<wens> MoeIcenowy: anything in particular?
<MoeIcenowy> wens: mostly based on your a80-psci
<MoeIcenowy> but adapted it for A83T
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<wens> I meant, anything in particular you want me to check?
<wens> I do not remember much about PSCI right now
<MoeIcenowy> I don't know either
<MoeIcenowy> as I'm also a newbie to PSCI
<MoeIcenowy> so I want someone experienced to check it ;-)
<wens> well, if you don't have something in particular you want checked or to ask
<wens> it won't be much of a priority for me right now, as I have to spend some time just refreshing my memory on it
<MoeIcenowy> maybe cpu_off code needs check, but as it doesn't work totally, there's no need to check it ;-)
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<wens> it doesn't work on my a80 either, though at one time it did :/
<MoeIcenowy> and you can check whether it can be adapted back again to a80
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<zoobab> do you know if the Pinebook screen line problem is fixed? I read it was a software issue
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<MoeIcenowy> jernej: can the A83T HDMI controller be descreambled?
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<jernej> MoeIcenowy: I think so, however, it has standard phy, so [U-Boot|Linux] driver has to be extended
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<MoeIcenowy> wens: could I send out your GIC workaround patch with my device tree binding & device tree changes?
<MoeIcenowy> (but maybe the A83T DTSI patch should be rebased on current linux-next as it's based on your a83t-ccu-mmc-usb now
<MoeIcenowy> (and I think I should cc stable for all kernel versions with A80/A83T DTSI file
<MoeIcenowy> (in this situation, patch 1~2 and 4 should be merged into 3.19+, and patch 3 should be merged into 4.6+
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<tllim> @zoobab, the Pinebook 11' screen flicker issue is software related and alraedy fixed. This case by the 11" LCD panel is 55Hz.
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<tllim> Thanks to Sunxi, we will up the mainline kernel experimental build for Pinebook soon.
<MoeIcenowy> tllim: what issue?
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<tllim> zoobab mentioned about 11" LCD flicker, ayufan alraedy fix on recent build
<MoeIcenowy> oh maybe I'm too dumb to find it ;-)
<tllim> thanks on your contribute so tyhat mainline build on Pinebook becomes possible
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<MoeIcenowy> P.S. the video codec driver is still blocking
<MoeIcenowy> although we now have the third vendor that fighting on stateless codecs -- ST
<MoeIcenowy> they developed a libv4l2 plugin to do stateless codec post process in userspace
<tllim> what is :satteless" codec?
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<nove> the principal difference is that a stateless hardware video codec engine, does not use a firmware
<tllim> @nove, thanks and good article on the "stateless" codec topic. This is new to me
<nove> in this case firmware, means software that needs to be loaded and runs in the hardware itself
<MoeIcenowy> nove: tllim is a hardware engineer and he of course knows firmware ;-)
<nove> because that hardware (video codec engine) doesnt have a hardware controller (where this firmware run)
<nove> the task of "controlling" the hardware (video codec engine), in this case of staleless is done by the linux kernel driver (in the cpu)
<KotCzarny> and i thought stateless would be that every frame has to be programmed anew
<tllim> @nove, thanks on the explanation. I thought stateless codec is a new concept :-)
<nove> yes that is also correct, because of no hardware controller every frame has to be set by the kernel driver
<KotCzarny> nove: how come there was a problem with concurrent decoding and encoding?
<KotCzarny> some state was apparently left there?
<nove> page 26 for a picture -> elinux.org/images/e/eb/Elc-20170223-v4l2-codec.pdf
<nove> or video of the talk -> https://www.youtube.com/watch?v=Y5P8CE9RtFs
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<nove> KotCzarny: from the maillist? (I must say that i did have time to look for the cause) but is very likely to be some problem in incomplete settting and clearing the right registers
<nove> (I must say that i did *NOT* have time to look for the cause)
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<KotCzarny> oh, wow, cnx blog is having bad day
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