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<
wens >
MoeIcenowy: I have no idea
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<
montjoie >
raaah still perf/4 for sun8i-ce (vs aes-generic)
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05:37
<
MoeIcenowy >
wens: I changed all GIC accesses to the aliased one, and now the system doesn't hang but say "CPUx: failed to come online"
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05:53
<
MoeIcenowy >
P.S. according to the BSP source code the mysterious sun8iw9 is a SoC with 6 CPU cores: 2 clusters, 3 cores per cluste
05:53
<
MoeIcenowy >
cluster
05:56
<
terra854 >
Did it say anything about what core does it have?
05:59
<
MoeIcenowy >
A7, of course ;-)
06:01
<
MoeIcenowy >
OK got quad core to run on A83T
06:02
<
MoeIcenowy >
wens: I'm now sure that the GIC problem not only exists on A83T, but also can totally block the PSCI to be used if not workarounded
06:02
<
wens >
yeah, exactly like the A80
06:02
<
MoeIcenowy >
let me make a GIC property for it
06:03
<
MoeIcenowy >
allwinner,secure-broken; ?
06:03
<
terra854 >
2 clusters of 3x A7?
06:04
<
terra854 >
I was thinking like a cluster of A15 and a cluster of A7
06:04
<
terra854 >
in a big.LITTLE configuration
06:04
<
MoeIcenowy >
that SoCs will be called sun9i instead of sun8i .
06:04
<
MoeIcenowy >
As it's named sun8iwx, it surely contains only A7
06:05
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06:07
<
MoeIcenowy >
wens: or should I make a more compatible for it? allwinner,sun9i-a80-gic ?
06:09
<
MoeIcenowy >
I don't think it's a bug by ARM, but a bug by Allwinner...
06:09
<
MoeIcenowy >
so maybe it will be better to call it allwinner,always-secure
06:10
<
wens >
the vendor for the GIC is ARM
06:10
<
terra854 >
Did anyone have an A80 device?
06:10
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06:10
<
MoeIcenowy >
terra854: wens ;-)
06:12
<
terra854 >
And did anyone got ahold of a H8vr device?
06:13
<
terra854 >
VR headset or SBC?
06:13
<
MoeIcenowy >
VR headset
06:13
<
MoeIcenowy >
H8vr should be just H8 -- it returns "A83T" in FEL
06:15
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06:21
<
terra854 >
I think that A83T and H8vr are one and the same...
06:24
<
MoeIcenowy >
and H8
06:27
<
olerem >
who is the right person to contact?
06:27
<
KotCzarny >
you have one in CC:, wens
06:28
<
olerem >
ok, thanks
06:29
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06:29
<
KotCzarny >
his nick is the same her, just fyi
06:29
<
olerem >
wens: ping
06:33
<
wens >
olerem: pong?
06:35
<
wens >
olerem: you have to send it to both maintainers
06:36
<
MoeIcenowy >
and for sunxi I think mostly Maxime Ripard merges the patches
06:36
<
wens >
olerem: I'm not the one picking up patches, though that will change beginning with the next cycle
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06:38
<
olerem >
oleksij@zwerg:~/tmp/linux$ ./scripts/get_maintainer.pl arch/arm/boot/dts/sun7i-a20-bananapi.dts | grep main
06:38
<
olerem >
Rob Herring <robh+dt@kernel.org> (maintainer:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS)
06:38
<
olerem >
Mark Rutland <mark.rutland@arm.com> (maintainer:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS)
06:38
<
olerem >
Russell King <linux@armlinux.org.uk> (maintainer:ARM PORT)
06:38
<
olerem >
Maxime Ripard <maxime.ripard@free-electrons.com> (maintainer:ARM/Allwinner sunXi SoC support)
06:38
<
olerem >
Chen-Yu Tsai <wens@csie.org> (maintainer:ARM/Allwinner sunXi SoC support)
06:38
<
olerem >
wens: both means?
06:39
<
olerem >
you and Maxime?
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06:43
<
olerem >
wens: ok. should i set your Acked-by?
06:44
<
MoeIcenowy >
wens: I will try to do octa-core on A83T now
06:45
<
MoeIcenowy >
as I'm based on your code I think it may be not so difficult to re-adapt it back to A80
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07:04
<
MoeIcenowy >
so strange... If I initialize CCI it will fail to boot...
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07:17
<
wens >
you have to bring up the cluster L2 caches before you enable CCI
07:17
<
wens >
otherwise it will hang waiting for transactions
07:27
<
MoeIcenowy >
I found it ;-)
07:27
<
wens >
if you want to be lazy, just initialize it before boot, like the original a83t psci series did
07:28
<
wens >
obviously the better way would be to initialize it when the cluster is brought up, and disable it if it is shut down
07:30
<
MoeIcenowy >
I think initialize it before boot is more proper ;-)
07:30
<
MoeIcenowy >
oh I found that sunxi_get_revision shouldn't be implemented as function, but should be a macro...
07:33
<
wens >
you can implement it as a function
07:33
<
wens >
you just have to make sure that __secure code only calls __secure code
07:33
<
MoeIcenowy >
thus I will need two copy of it
07:34
<
MoeIcenowy >
(because I want to print the revision number during boot, as it really matters
07:34
<
MoeIcenowy >
(and it may furtherly be used more
07:34
<
MoeIcenowy >
oh the A83T FEL load speed is so slooooooow...
07:36
<
MoeIcenowy >
wens: your workaround seems to have some problem -- if PSCI is not present it will lead to system panic
07:36
<
MoeIcenowy >
(GIC workaroud
07:38
<
wens >
yeah, i just fixed it
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<
wens >
oops, think I broke something again
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08:02
<
wens >
updated, though it still doesn't work well to unplug cores
08:02
<
wens >
it just hangs
08:04
<
MoeIcenowy >
oh the cluster 1 cpus do not want to start...
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<
wens >
MoeIcenowy: there is a reason I put that on hold
08:53
<
MoeIcenowy >
wens: ;-)
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10:15
<
montjoie >
how to change bus_ce clock to 300Mhz ? clk_set_rate() end with success but no change
10:15
<
montjoie >
does I need to reparent to pll-periph0 ?
10:16
<
wens >
you cannot change bus_* clock
10:16
<
wens >
do you mean ce clock?
10:17
<
montjoie >
in /sys/kernel/debug/clk/clk_summary it is bus-ce
10:17
<
montjoie >
ahb1_ce in DT
10:17
<
wens >
the bus clocks are not designed to be changed, as the bus is shared
10:18
<
montjoie >
the datasheet said CE clk could be up to 300, so I expect better performance
10:18
<
wens >
there is another "ce" clock
10:18
<
wens >
that is the module clock
10:18
<
montjoie >
yes the "mod" clock but it is already at max
10:19
<
wens >
how can that be
10:19
<
wens >
what platform are you working on
10:21
<
wens >
a64 manual 1.0, page 109/110
10:21
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10:21
<
wens >
the CE clock can definitely go above 24 MHz
10:22
<
montjoie >
oups wrongly read >=
10:24
<
montjoie >
so I could tyr 48Mhz ?
10:24
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10:25
<
montjoie >
but the parent is already at max 24Mhz
10:25
<
wens >
it can be muxed to pll-periph-2x
10:25
<
wens >
just set a higher rate, like 200 MHz, and it will switch over
10:37
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10:46
<
BenG83 >
codekipper, did tllim get in touch with you?
10:50
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11:08
<
karak >
Hi, to All! Please, tell me, how I can adjust of R_UART baud rate? I have output from R_UART on custom board based on A80. I see a garbage on linux terminal and try all of them (9600, 19200, ... 115200) with the same result.
11:10
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11:18
<
KotCzarny >
nice. libvdpau-sunxi is going to be updated soon, with fixed color space and stuff, already working great
11:20
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11:27
<
oliv3r >
wens: thanks for pointing out my oversight :)
11:29
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11:33
<
BenG83 >
!seen ssvb
11:36
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11:37
<
oliv3r >
wens: my confusion probably came from the fact, that th eDW_UART_USR define is 8bit aligned, and immediatly following that define, we have the DW_UART_CPR and UCV defines, which are 32bit aligned.
11:37
<
montjoie >
wens: what is the maximum safe value ?
11:38
<
ElBarto >
diego_r: yep
11:40
<
diego_r >
Hi ElBarto / Emmanuel. I'd like to get the above patch finished and upstreamed. Are you the original author of the patch? How do you want to be credited?
11:40
<
ElBarto >
diego_r: yes I'm the original author, I was sure that I did resend it or that someone else did ...
11:41
<
montjoie >
wens: very very little increase at 200Mhz
11:42
<
ElBarto >
diego_r: ok, well if you want to finish the work be my guest
11:44
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11:45
<
MoeIcenowy >
wens: 7 core succeeded
11:46
<
MoeIcenowy >
the cluster 1 core 0 has some different behavior on Rev.A and Rev.B on A83T so I will soon enable it
11:47
<
oliv3r >
i think i even sent a emmc defconfig for the lime2 at some point
11:47
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11:47
<
oliv3r >
maybe i'm confused
11:48
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11:48
<
oliv3r >
diego_r: are you going to resend it?
11:48
<
oliv3r >
otherwise i'll git send-email mine, as I have it locally committed already anyway
11:49
<
diego_r >
ElBarto: as you prefer. Do you want to me go on or do you prefer to finish what you started?
11:49
<
oliv3r >
i think it was not merged back then, as it needed some rework and the dts wasn't merged yet
11:49
<
ElBarto >
diego_r: check with oliv3r, if he have a patch that he's using maybe it's best if he send it
11:50
<
ElBarto >
oliv3r: dts was wrong on the emmc pins anyway
11:50
<
ElBarto >
I don't remember when I fixed that, maybe january ?
11:51
<
oliv3r >
ElBarto: is u-boot not usign the upstream dts; so the pins should be right no?
11:51
<
diego_r >
oliv3r: ElBarto: three guys for one tiny change are too many :) Let's just figure out who's ahead with this one and then decide.
11:52
<
ElBarto >
ah no it wasn't the pins
11:53
<
oliv3r >
ah the pwrseq bit
11:53
<
BenG83 >
did BSD projects get Pinebook samples?
11:53
<
wens >
MoeIcenowy: seems max is 400 MHz, according to the manual
11:53
<
oliv3r >
yeah i actually removed it from my local set as it didn't work :)
11:53
<
ElBarto >
BenG83: we should received some soon I hope
11:53
<
BenG83 >
ping me if there are any issues
11:53
<
wens >
MoeIcenowy: that bit is stupid, why would they change that between revisions
11:55
<
ElBarto >
BenG83: and that's for FreeBSD, don't know about the others
11:55
<
MoeIcenowy >
wens: I don't lnow it
11:56
<
MoeIcenowy >
wens: are you replying montjoie with 400MHz?
11:56
<
wens >
MoeIcenowy: it was a rhetorical question...
11:56
<
wens >
MoeIcenowy: oops, yeah
11:56
<
montjoie >
wens: sure that's impossible to put bus_clk to 300 ?
11:56
<
wens >
montjoie: maybe DMA can't keep up?
11:57
<
wens >
montjoie: you could do it in U-boot, but I recommend not touching the bus clocks once in Linux
11:57
<
MoeIcenowy >
In fact the only error that prevented me from getting cluster1 to work is wrongly setting the length of cpu_pwr_clamp array in PRCM
11:57
<
ElBarto >
oliv3r: will you take care of sending this defconfig ?
11:57
<
MoeIcenowy >
but I didn't cherry-pick your cpu_off commit now, only cpu_on is supported
11:59
<
oliv3r >
ElBarto: sure
12:00
<
diego_r >
ok. oliv3r, let me know if you need any helping hand
12:01
<
MoeIcenowy >
wens: but the newest user manual of A83T showed only the situation of Rev.B
12:01
<
oliv3r >
actually its kinda good your version wasn't merged back then, it still uses the old (and crashing) 480 Mhz
12:01
<
MoeIcenowy >
oh hooray "smp: Brought up 1 node, 8 CPUs"
12:01
<
oliv3r >
i will actually add it to my changeset that implements the AXP LDO3 fix
12:01
<
oliv3r >
hmm, maybe not; i'l send it first
12:01
<
oliv3r >
as i have to do some work on that sent
12:02
<
MoeIcenowy >
P.S. My chip is Rev.B, and I don't know who has a Rev.A
12:02
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12:08
<
MoeIcenowy >
wens: what's the CPUID number format of ((readl(GICC_BASE + GICC_IAR) >> 10) & 0x7) ?
12:09
<
MoeIcenowy >
is it in mpidr format (0x100 for cluster 1 core 0) or is it in dense format (0x4 for cluster 1 core 0)?
12:09
<
wens >
the GIC only has 8 interfaces, and they are numbered 0~7
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12:14
<
MoeIcenowy >
ok CPU hotplugging doesn't work well here on A83T
12:14
<
MoeIcenowy >
even in cluster 0
12:18
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12:18
<
oliv3r >
diego_r: done
12:20
<
MoeIcenowy >
wens: you can enable BPi M3 usb_otg in peripheral-only mode now in your branch
12:20
<
MoeIcenowy >
that is useful
12:20
<
diego_r >
oliv3r: seen the email. Nice, thanks
12:20
<
MoeIcenowy >
rather than leave them disabled
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<
wens >
MoeIcenowy: I had a patch doing that
12:50
<
wens >
or was it for host mode
12:52
<
MoeIcenowy >
you only enabled h8homlet evb as host mode
12:52
<
MoeIcenowy >
and the other 2 boards (bpi-m3 and ct+) have usb_otg left disabled
12:54
<
wens >
not really a priority for me now though
12:56
<
parazyd >
load mmc 0:1 0x43000000 ${fdtfile} || load mmc 0:1 0x43000000 boot/${fdtfile}
12:56
<
parazyd >
the ${fdtfile} here is a path, right? so it can be also: dtbs/${fdtfile} ?
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12:59
<
MoeIcenowy >
wens: could you look at my a83t psci code?
13:06
<
parazyd >
wens: thx
13:08
<
wens >
MoeIcenowy: anything in particular?
13:11
<
MoeIcenowy >
wens: mostly based on your a80-psci
13:12
<
MoeIcenowy >
but adapted it for A83T
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13:14
<
wens >
I meant, anything in particular you want me to check?
13:14
<
wens >
I do not remember much about PSCI right now
13:14
<
MoeIcenowy >
I don't know either
13:14
<
MoeIcenowy >
as I'm also a newbie to PSCI
13:15
<
MoeIcenowy >
so I want someone experienced to check it ;-)
13:16
<
wens >
well, if you don't have something in particular you want checked or to ask
13:16
<
wens >
it won't be much of a priority for me right now, as I have to spend some time just refreshing my memory on it
13:17
<
MoeIcenowy >
maybe cpu_off code needs check, but as it doesn't work totally, there's no need to check it ;-)
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<
wens >
it doesn't work on my a80 either, though at one time it did :/
13:18
<
MoeIcenowy >
and you can check whether it can be adapted back again to a80
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14:37
<
zoobab >
do you know if the Pinebook screen line problem is fixed? I read it was a software issue
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<
MoeIcenowy >
jernej: can the A83T HDMI controller be descreambled?
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<
jernej >
MoeIcenowy: I think so, however, it has standard phy, so [U-Boot|Linux] driver has to be extended
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<
MoeIcenowy >
wens: could I send out your GIC workaround patch with my device tree binding & device tree changes?
18:00
<
MoeIcenowy >
(but maybe the A83T DTSI patch should be rebased on current linux-next as it's based on your a83t-ccu-mmc-usb now
18:01
<
MoeIcenowy >
(and I think I should cc stable for all kernel versions with A80/A83T DTSI file
18:03
<
MoeIcenowy >
(in this situation, patch 1~2 and 4 should be merged into 3.19+, and patch 3 should be merged into 4.6+
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18:10
<
tllim >
@zoobab, the Pinebook 11' screen flicker issue is software related and alraedy fixed. This case by the 11" LCD panel is 55Hz.
18:10
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18:11
<
tllim >
Thanks to Sunxi, we will up the mainline kernel experimental build for Pinebook soon.
18:11
<
MoeIcenowy >
tllim: what issue?
18:11
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18:12
<
tllim >
zoobab mentioned about 11" LCD flicker, ayufan alraedy fix on recent build
18:12
<
MoeIcenowy >
oh maybe I'm too dumb to find it ;-)
18:13
<
tllim >
thanks on your contribute so tyhat mainline build on Pinebook becomes possible
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18:20
<
MoeIcenowy >
P.S. the video codec driver is still blocking
18:20
<
MoeIcenowy >
although we now have the third vendor that fighting on stateless codecs -- ST
18:22
<
MoeIcenowy >
they developed a libv4l2 plugin to do stateless codec post process in userspace
18:25
<
tllim >
what is :satteless" codec?
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18:30
<
nove >
the principal difference is that a stateless hardware video codec engine, does not use a firmware
18:31
<
tllim >
@nove, thanks and good article on the "stateless" codec topic. This is new to me
18:32
<
nove >
in this case firmware, means software that needs to be loaded and runs in the hardware itself
18:32
<
MoeIcenowy >
nove: tllim is a hardware engineer and he of course knows firmware ;-)
18:33
<
nove >
because that hardware (video codec engine) doesnt have a hardware controller (where this firmware run)
18:34
<
nove >
the task of "controlling" the hardware (video codec engine), in this case of staleless is done by the linux kernel driver (in the cpu)
18:35
<
KotCzarny >
and i thought stateless would be that every frame has to be programmed anew
18:38
<
tllim >
@nove, thanks on the explanation. I thought stateless codec is a new concept :-)
18:38
<
nove >
yes that is also correct, because of no hardware controller every frame has to be set by the kernel driver
18:39
<
KotCzarny >
nove: how come there was a problem with concurrent decoding and encoding?
18:39
<
KotCzarny >
some state was apparently left there?
18:39
<
nove >
page 26 for a picture -> elinux.org/images/e/eb/Elc-20170223-v4l2-codec.pdf
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<
nove >
KotCzarny: from the maillist? (I must say that i did have time to look for the cause) but is very likely to be some problem in incomplete settting and clearing the right registers
18:43
<
nove >
(I must say that i did
*NOT* have time to look for the cause)
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<
KotCzarny >
oh, wow, cnx blog is having bad day
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