Turl changed the topic of #linux-sunxi to: Allwinner/sunxi /development discussion - did you try looking at our wiki? https://linux-sunxi.org - Don't ask to ask. Just ask and wait! - https://github.com/linux-sunxi/ - Logs at http://irclog.whitequark.org/linux-sunxi
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<willmore> 45 pounds for that board? That's quite a bit.
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<MoeIcenowy> montjoie: maybe it put a PHY designed as 1000Mbps there, then tested, but found the performance is much low than 1000Mbps, then named it 100Mbps
<wens> oops
<MoeIcenowy> wens: ?
<willmore> ssvb, have you ever used an esp8266? They use SPI NOR flash to XIP. They have a little header that says what kind of I/O mode to use with the chip and what clock speed to use. It's not horribly flexible, but it seems to work for them.
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<willmore> Yikes. Reading the datasheet for the Winbond NAND flash SPI chip I will say that I hope no one uses one of these for code. If you use them with chip ECC on, they you can close your eyes and hope everything works right. If not, you want to do ECC in the SoC and do proper bad block management.
<MoeIcenowy> the bad block management cannot be offloaded to SPI chip, right?
<willmore> This makes me think that the right way to use these might just involve a block table like LILO used to use--give the loader a list of blocks to read in the order they should be read to make up the image. Then let some smart piece of code run in user land to compose that list.
<willmore> MoeIcenowy, it can, but it's not horribly robust.
<willmore> The 128MB Winbond chip has 2K page size and can handle up to 4 bit errors in each block. If it goes beyond that you can map the block out with a 20 entry LUT. Once the LUT is full, there's nothing more the chip can do to help you.
<willmore> Oh, and they specify that it's completely fine for them to ship you a chip with all 20 bad blocks already programmed. That leaves zero room to grow the bad block list.
<MoeIcenowy> have you read the link I provided you several hours ago?
<MoeIcenowy> (the GigaDevice one
<willmore> No, let me check it.
<willmore> Did you mean the datasheet for the chip used in the Lichepi?
<MoeIcenowy> yes
<MoeIcenowy> but I talked to the author, and he may change the behavior in future versions
<willmore> How are they using it now? Letting the chip manage the ECC?
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<MoeIcenowy> montjoie: I tried to change phy_mode to rgmii and the internal_phy property in sun8i-emac to RGMII thing.
<MoeIcenowy> The network is still 100Mbps
<MoeIcenowy> sun8i-emac 1c30000.ethernet eth0: Link is Up - 100Mbps/Full - flow control rx/tx
<willmore> MoeIcenowy, if anything that GC chip is worse. It has the same spec for bad blocks--and the same way of marking them--but it seems to lack the LUT which would allow it to patch around them.
<willmore> So, you could have a fault in the early part of the chip and not even be able to program a header for the BROM to see.
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<MoeIcenowy> lichee pi choose to rely on my mainlineing work of V3s
<MoeIcenowy> so they have now no system images ;-)
<MoeIcenowy> currently everything runs on SD
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<willmore> I wish them luck.
<MoeIcenowy> in fact currently the hardware designer is only one person ;-)
<willmore> That's a real small operation.
<MoeIcenowy> but lichee pi zero is still something meaningful ;-)
<MoeIcenowy> although now I found my relationship with him is a bit like Free Electrons and Next Thing Co ;-)
<willmore> I didn't say it wasn't. I just know how hard it is to produce something like this.
<MoeIcenowy> yes it's really hard
<MoeIcenowy> but I still wonder if a hardware vendor choose to use mainline is a good thing
<MoeIcenowy> we still lack the CSI support fully
<MoeIcenowy> especially for sun6i generation CSI no one have worked yet
<willmore> Yeah, going for mainline--while a good goal--might be a lot more work than they're ready for.
<dr1337> MoeIcenowy: we're going to be using mainline in our product
<willmore> Hey, on the plus side, there's no legacy code to work around. ;)
<MoeIcenowy> V3s is a camera-oriented SoC
<MoeIcenowy> but we still have no CSI support
<MoeIcenowy> (although I have not even got a camera suitable for using on the board ;-)
<MoeIcenowy> maybe CSI is the most difficult part currently on V3s :-)
<MoeIcenowy> willmore: yes... the V3s BSP is kind of sh*t
<willmore> MoeIcenowy, any data from Allwinner?
<MoeIcenowy> willmore: what do you want?
<MoeIcenowy> the sh*t BSP of V3s that even myself do not use? ;-)
<MoeIcenowy> oh I must go
<MoeIcenowy> bye
<willmore> No, I meant have you received any data from Allwinner on how the CSI works so you can implement it.
<willmore> Later.
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<willmore> I take it back, GC promises the first block will not be spared out when new. :) Yah. It is completely fine if it fails right after you start using it, though. ;)
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<MoeIcenowy> willmore: I can get nothing ;-)
<MoeIcenowy> except the datasheet, which I got even before get Lichee Pi Zero
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<scream> hey! does anyone have a mainline tree at github with working audio and network?
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<codekipper> scream: which SoC?
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<rellla> must sun4i/sun8i drm/kms driver kick out simplefb, or can they work in parallel?
<rellla> *stay in parallel
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<Net147> rellla: I think the DRM driver resets the display pipeline so they can't work in parallel without changing the driver to configure itself based on the current state instead of resetting
<rellla> Net147: must i disable one of them in my kernel config?
<Net147> rellla: the DRM driver should automatically kick out simplefb and take over
<Net147> rellla: as long the as the device tree is configured properly
<rellla> which means?
<Net147> rellla: it depends what board you are using. only some are configured to use DRM out of the box.
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<Net147> rellla: which board are you working on?
<rellla> Net147: currently i'm using H3 OPi+, configured with simple_fb and display-drm marked "Y"
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<Net147> rellla: HDMI display?
<rellla> yes.
<Net147> rellla: HDMI is not supported by DRM driver yet
<rellla> and this is my dmesg http://pastebin.com/R8YkDiv8 , which leeds me to the conclusion, that not everything is fine with display/simplefb regarding line 142
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<rellla> now i wonder if it's because of the coexistence of both or because have to enlarge my cma pool size first :p
<Net147> rellla: you can try enlarging CMA size
<rellla> yeah, i must. dicussed that already yesterday. we will see. if it's not working, i will come up again with my question :p
<Net147> rellla: you can try CONFIG_CMA=y, CONFIG_CMA_SIZE_MBYTES=256, CONFIG_DMA_CMA=y
<rellla> Net147: ok, will try
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<jernej> rellla: You have to disable one of them I think
<jernej> I think that DRM driver is missing something like this: https://github.com/torvalds/linux/blob/master/drivers/gpu/drm/sun4i/sun4i_drv.c#L100-L114
<rellla> jernej: thanks. maybe i'll do a quick hack into h3-drm
<rellla> *sun8i-drm
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<MoeIcenowy> montjoie: do you have a way to test sun4i-ss?
<MoeIcenowy> I want to test sun4i-ss on V3s now
<montjoie> MoeIcenowy: with https://github.com/montjoie/cryptotest
<MoeIcenowy> montjoie: "sun4i-ss 1c15000.crypto-engine: Die ID 7" is it an expected dmesg output?
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<MoeIcenowy> montjoie: /home/icenowy/git-repos/cryptotest/kernel/cryptotest.c:133:8: error: implicit declaration of function 'crypto_alloc_ablkcipher' [-Werror=implicit-function-declaration]
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<montjoie> MoeIcenowy: I have a fix to push for that
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