Turl changed the topic of #linux-sunxi to: Allwinner/sunxi /development discussion - did you try looking at our wiki? https://linux-sunxi.org - Don't ask to ask. Just ask and wait! - https://github.com/linux-sunxi/ - Logs at http://irclog.whitequark.org/linux-sunxi
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<apritzel> does anybody have an idea of what this "MBUS" actually is in those Allwinner SoCs?
<apritzel> I see it mentioned, but never explained in the manuals
<apritzel> apparently it is somehow connected to some DMA and/or DDR-RAM, but how remains unclear
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<wens> apritzel: i'm guessing some sort of arbitration bus?
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<ErwinH> The dtb added in to the u-boot defines the settings of the board. Altering the rx-delay in the u-boot dtb breaks the connection.
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<Pe3ucTop> Hello to all, could anyone comment on clock and serial drivers behaviour ?
<Pe3ucTop> What I try to do is speed up serial port, so 2 things : change clock source and it's frequency , and get stable serial port.
<Pe3ucTop> On clock I got source changed, but can't change frequency , got some type crash:
<Pe3ucTop> which report apb1 can't set apb1 clk rate.
<Pe3ucTop> and still clk source got changed to PLL6
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<Pe3ucTop> But strange behaviour is with serial, in standart boot up it is shown as "is a U6_16550A", but in speeded up situation as: "is a 16550A"
<Pe3ucTop> who now, what is difference between 16550A and U6_16550A ??
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<codekipper> Hi All, if anybody is interested I have a branch here that has working I2S, HDMI (audio and video) and analog codec on the H3. https://github.com/codekipper/linux-sunxi/commits/sunxi-wip
<codekipper> SPDIF should also work but I've not verified properly(have a Beelink X2 on order).
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<fossxplorer> Hi folks. I'm looking to buy a 1gbit based S905 based Android device to run Linux (Armbian). Things changed a bit lately and Mini MXIII with S905X doesn't come with gbit anymore. Ḯ'm now planning to buy http://www.ebay.com/itm/172136997918. Just wondering if i could get Linux running on this in the future..
<KotCzarny> isnt this offtopic? check soc?
<fossxplorer> My apologies if it's OT!
<KotCzarny> you might check s905/s905x support status
<jelle> fossxplorer: there is a channel for amlogic stuff it's #linux-amlogic, but not much active
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<fossxplorer> Ok, thanks!
<tkaiser> fossxplorer: I don't get it. Since you already mentioned Armbian why not looking into Armbian forum. There is an own Amlogic subforum and as far as I remember nearly every S905 box out there is supported (after DT tweaks)
<fossxplorer> tkaiser, i was unable to find this model there. Will possibly post there. Thanks!
* fossxplorer wondering if Armbian also has an IRC channel.
<KotCzarny> it has a forum
<KotCzarny> :)
<fossxplorer> .)
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<tkaiser> ErwinH: Regarding your .dtb comment... this was about OPi PC 2 and 'Buddy' images? Does this mean testing with apritzel's peekpoke doesn't work on your board?
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<msevwork> tkaiser do you maybe know what currently work for orange pi zero in armbian (does wifi and ethernet work)? what doesnt work?
<msevwork> works*
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<tkaiser> msevwork: With legacy kernel everything works. We have some reports WiFi would be slow and dpg has the theory that interrupts are the culprit. I can't test any more (WiFi broken) and literally no one had a look whether the claim is true or not. I got a bit sick of this stuff in the meantime
<msevwork> is legacy the default kernel that comes with the opizero armbian image?
<msevwork> why aren't you guys on the #armbian freenode channel also?
<tkaiser> msevwork: With mainline kernel also everything should work except of WiFi. But that's just throwing https://github.com/halmartin/linux/commit/4a93b9450a6d563b1e5e469c960c6c5430220bef.patch into userpatches dir (and adding .dts). But no one takes care, I can't test and I don't give a sh*t any more :)
<msevwork> why?
<ErwinH> tkaiser: Yes, peekpoke works, but I was looking for the reason why the .dtb settings weren't applied and which settings were. It uses the .dtb found in the u-boot and it appears it skips the .dtb found on the FAT32 image on the buddy image's.
<msevwork> are you mad at someone tkaiser :D
* jelle thought icenowy had an orange pi zero wifi fork which works
<tkaiser> ErwinH: So everything as expected.
<ErwinH> Correct
<tkaiser> jelle: dpg's repo might be a bit more polished in the meantime: https://github.com/fifteenhex/xradio
<msevwork> wait so i have two options to choose when i download the opi0 images, either the mainline or the legacy kernel
<KotCzarny> tbh for a desktop/browser/media box machine i found self build android quite nice
<KotCzarny> *built
<jelle> tkaiser: no clue
<msevwork> tkaiser why don't you give a sh*t about opi0 anymore :D
<tkaiser> msevwork: No, you don't have this option. It sucks a bit. No useful user feedback when you ask for and only complaints since people want to use beta stuff productive.
<msevwork> yeah i understand you, but i prolly wouldn't be much help since I'm a noob :D
<msevwork> i'd have to ask too much questions
<msevwork> tho' if you say wifi, ethernet and gpio should work I could maybe try and make a sprinkler system out of an opi0
<msevwork> or maybe just use opi pc+ and be sure that everything will work :)
<tkaiser> msevwork: Well, it's a huge investment so be careful!1!! ;) Personally I will order 2 more OPi Zero and will then run 4.9 on them. Am reading through http://www.brendangregg.com/blog/2016-10-27/dtrace-for-linux-2016.html (this is real fun, not playing unpaid 1st level supporter somewhere in a forum).
<msevwork> haha
<msevwork> well you were good in the forums, much respect for that!
<dgp> jelle: my original branch of the xradio driver works pretty well. One time out of 20 or something the firmware does crash.. I already know what that is though
<jelle> dgp: oh I don't have a pi zero :p
<msevwork> great dgp so you'll make it 100% reliable :D
<dgp> msevwork: The driver needs to be re-written. I started doing that but the firmware crashes so I'm trying to clean up the original driver as much as possible first
<tkaiser> dgp: Do you have any plans to do the re-write to be able to send the driver upstream? Or hoping for others (Hans ;) ?
<dgp> no plans for upstream. If I can get client + ap mode working in the original driver I might even live with that
<dgp> Maybe some of the guys messing around with those ESP things will see it as a better option for a lot of projects and help out.. :D
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<willmore> dgp, the esp8266 is pretty hand and cheap and useful for a lot of stuff. It is a pretty constrained environment--nothing like a full up Linux distro. I'm sure the things they can solve will overlap a lot with the OpiZ, but the skill needed to do so will differ a great deal.
<willmore> People with Linux experience will find the OpiZ much easier than the esp8266.
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<dgp> willmore: I have a little setup that spits out a buildroot based setup that supports OTA etc and can be flashed to a 16mb SPI nor for the pi zero..
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* nove has this last 2 weeks to read
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<nove> there is given too much importance to "rootmydevice", which wasn't any more than a debug feature that was accidentally enabled, when there are others issues (of source-code functionality) that are more of concern and serious real evil, (but this ones nobody talks)
<nove> if is to criticize source-code quality, then "rootmydevice" is not a good example
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<willmore> dgp, that sounds cool!
<jski> which is the better kernel to use for the H3 soc?
<KotCzarny> 4.10
<jelle> depends on what you want
<willmore> Sounds like the ability to make SPI NOR enabled allwinner boards net boot is moving along nicely. yay!
<dgp> willmore: It boots completely from NOR with my setup
<jski> for now stable networking, usb and emmc
<willmore> dgp, mount root over the network?
<KotCzarny> then even plain 4.9 will suffice for you
<jski> uart too :/
<willmore> emmc is stable in mainline?
<dgp> willmore: nope. There are two complete sets of device tree, kernel and rootfs on the 16MB flash
<willmore> Or is that 'stable, but not backwards compatable'?
<KotCzarny> emmc is almost the same as sd
<willmore> dgp, Oh, 16MB flash, you said 16mb before. I would love to see someone get a while system in 2MB.
<dgp> willmore: sorry, 16MB chips are only $1 or so each though.. You could get u-boot and a kernel into 2MB maybe
<willmore> dgp, agreed. I bought a few a while back to do this kind of testing. Then I misplaced them.... I'll find them eventually.
<jski> so orangepi only release their own version of 3.4?
<jelle> jski: yes
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<willmore> the 2MB value seems to be a reasonable target for a BIOS like setup with net boot and various DTB manipulating things.
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<jski> will try their kernel then mainline
<dgp> willmore: putting u-boot in spi nor for recovery would be good. The SPL boots from sd card if you have it inserted too so it doesn't really break anything
<willmore> dgp, yep. it just adds a level of ease for new users--put in a blank uSD and power it on and it'll download a distro and burn it. ;) Okay, that may be going to far, but it sounds nice.
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<dgp> willmore: or you have an os setup on the flash and it goes and grabs your IoT python or whatever script from your account and just runs
<dgp> willmore: no messing around with stupid little microcontroller that can barely do TLS properly
<jski> In the https://linux-sunxi.org/Orange_Pi_PC Xunlong says it can boot from SD, NAND or NOR flash so asuming that include emmc?
<dgp> SD and eMMC are basically the same thing
<jski> yes but can never be sure :P
<dgp> one is in a card, one is in a chip
<jski> gmac "Somebody works on it and the result is mostly stable enough"
<jski> worrying :/
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<dgp> source code is out there if you want to help fix it ;)
<jski> I might but need to set up a test for Thursday so will use the orangepi kernel then try schedule some time
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<jski> I will need it at some point :)
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<jski> the last ethernet driver I worked on was smsc9112 on the imx21 :D
<jski> kenrel 2.1.16 I think
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<KotCzarny> gmac was almost done, then something unexpected turned out, now it need a rewrite before can be mainlined
<KotCzarny> but you can use that patch
<montjoie> :)
<MoeIcenowy> KotCzarny: modified dwmac for sun8i-gmac?
<KotCzarny> most likely
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<willmore> dgp, or can only do an outdated version of TLS, etc. Agreed.
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<jski> have tried this example http://www.orangepi.org/orangepibbsen/forum.php?mod=viewthread&tid=845 and nothing shows in serial console. should the latest u-boot work with Orangepi_defconfig on the orange pi pc plus?
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<KotCzarny> the only forum you should use is armbian
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<KotCzarny> jski: grab armbian build script, create kernel/modules + uboot, then apply to some arm arch image
<KotCzarny> and done
<jski> I only need u-boot
<KotCzarny> do you need hdmi?
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<jski> not yet
<KotCzarny> then plain mainline uboot will do
<KotCzarny> and for opipc you should use oirangepipc_defconfig
<KotCzarny> right?
<KotCzarny> because original orange pi was a20 based, and opipc is h3 based
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<KotCzarny> orangepi_pc_defconfig
<KotCzarny> ls configs |grep -i orange
<jski> ah that be why
<jski> there is a orangepi_plus_defconfig and orangepi_pc_defconfig
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<jski> well that and latest is not latest.. 2017.01-rc1 has a orangepi_pc_plus_defconfig
<KotCzarny> you've said you have opipc, not opipc+
<jski> actually I have both :P
<jski> and the plus 2
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<KotCzarny> last time i've compiled uboot for opipc it booted on opi+2e too
<KotCzarny> so its not that important
<KotCzarny> unless you need specific features, ie. usb
<KotCzarny> but for plain microsd boot one will suffice
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<jski> https://bpaste.net/show/f9664f6b5891 now it is complaining about the dtb and kernel not existing weird
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<Pe3ucTop> Hello once again, do anybody knoh how to change APB1 clock frequency correct way?? I see it's initialized in uBoot , but I need to change it in kernel ?
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<MoeIcenowy> jernej: have you sent out your patches?
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<apritzel> Pe3ucTop: on which SoC is this?
<apritzel> Pe3ucTop: because on the H3 and A64 the UART is driven by APB2, which can be clocked independently from APB1
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<jernej> MoeIcenowy: Not yet, I have issues with patman. I must find out why it doesn't wan't to produce patches
<apritzel> Pe3ucTop: and actually the common clock framework should be able to work that out for you automatically, so you could just try to set a higher baudrate, and once you exceed 1.5Mbps it should switch to Periph0 automatically
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<MoeIcenowy> apritzel: how is the situation of mmc now?
<apritzel> MoeIcenowy: looking good for me, the BPi-M64 is quite happy
<MoeIcenowy> still with ugly hacks?
<MoeIcenowy> or you finally tidy up them?
<apritzel> MoeIcenowy: I will probably post a new branch based on 4.9 very soon
<MoeIcenowy> without mmc the system can barely be usable...
<apritzel> MoeIcenowy: no, mripard fixed it correctly
<MoeIcenowy> oh good work ;-)
<MoeIcenowy> will it be scheduled for 4.11?
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<apritzel> MoeIcenowy: I hope so, but it's a small fix only, really, so should be no problem
<apritzel> MoeIcenowy: the SDHC2 controller can only cope with 8K of DMA at once, not with 64K as the other two
<MoeIcenowy> ah-oh
<apritzel> MoeIcenowy: which is of course not mentioned in the manual ...
<MoeIcenowy> mysterious answer...
<apritzel> hdparm gives me a decent 40MB/s for the eMMC on the BPi
<MoeIcenowy> I think I'm not going to purchase a Banana Pi M64 at all ;-)
<apritzel> it's a nice little board, really
<apritzel> actually more decent than the Pine64 ;-)
<KotCzarny> :)
<apritzel> it has a barrel plug power connector, a FEL button, proper uUSB for OTG, eMMC, soldered reset & power buttons ...
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<Pe3ucTop> apritzel: Thanks, I use R8 (~ A13 ) , and I tried to use different rates, but driver serial driver initilised to base rate 1.5M
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<Pe3ucTop> I tried to setup APB1 to needed frequency in Device tree, but got error, :(
<tkaiser> apritzel: Did you test write speed also on the eMMC? I ask since someone testing BPi M2 Ultra (most likely same eMMC) got 40 MB/s read and amazing 6 MB/s write ;)
<apritzel> tkaiser: that is expected
<tkaiser> apritzel: Huh?
<apritzel> tkaiser: this is the smallest and cheapest eMMC Samsung seems to sell
<tkaiser> apritzel: LOL, can't believe it.
<KotCzarny> at least its not noname
<KotCzarny> ;)
<KotCzarny> and not mlc ? ;)
<apritzel> this particular chip gives max 100MB/s while reading and really 6 MB/s writing
<tkaiser> apritzel: With BPi M3 and M2+ they read rates of ~80 MB/s and above 20 MB/s writing.
<apritzel> tkaiser: yes, the M3 uses the "high performance eMMC-Pro" version
<apritzel> the M64 only the "Standard eMMC"
<apritzel> the first one is specified as 180/20, the latter as 100/6
<tkaiser> apritzel: And this crappy board costs me 56,-Û here in DE. No, thanks :)
<apritzel> I expect the read performance still to improve over time
<KotCzarny> but having os there isnt better than on class6 card
<KotCzarny> unless to treat it as a big uboot+kernel sotrage
<KotCzarny> *storage
<apritzel> KotCzarny: for a pure OS partition write performance doesn't matter so much
<KotCzarny> logs?
<KotCzarny> /var/run ?
<apritzel> if you write more than 6MB/s in /var you have other issues ...
<KotCzarny> bad example, /var/cache is better
<tkaiser> apritzel: Do you have a distro running? Care to try out an iozone call to get an idea how random IO performance behaves? According to your PDF it's also low as hell.
<KotCzarny> but that's 6MB/s random io or seq?
<apritzel> tkaiser: I have Ubuntu 14.04 and 16.04 installed
<apritzel> tkaiser: so yes, I can easily apt-get or compile stuff
<tkaiser> apritzel: Depends on the use case. Android or Desktop Linux write constantly and this is all random IO (browsers).
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<tkaiser> apritzel: It's an 'apt-get install iozone3' and then...
<KotCzarny> tkaiser, i run android off sdcard, its manageable
<apritzel> tkaiser: sure, will try later tonight
<KotCzarny> as soon as you turn off disk cache in firefox
<apritzel> what's a desktop?
<apritzel> :-D
<KotCzarny> thing that lays on your desk
<BurtyB> no that's a keyboard
<apritzel> I put my boards on one, indeed
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<KotCzarny> if you put sbc on your lap, then its a laptop
<KotCzarny> but requires monitor there too
<tkaiser> iozone -O -i 0 -i 1 -i 2 -e -+n -r 4K -s 2000m and iozone -e -I -a -s 100M -r 4k -r 16k -r 512k -r 1024k -r 16384k -i 0 -i 1 -i 2
<apritzel> tkaiser: cheers, saves me some time
<apritzel> gotta run now ...
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<Pe3ucTop> Could someone describe clock setup in kernel Device Tree? I tried to apply debug to clock initialisation, and it's look like all clock get registered with 0 rates and after get updated.. Because of thet I can't understand how to init clock.
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<alain__> For some reason, my Orange PI PC Plus is only connecting half duplex. Using latest 4.9-rc kernel + patches from Megous tree.
<alain__> [ 1248.820559] sun8i-emac 1c30000.ethernet eth0: Link is Up - 100Mbps/Half - flow control off
<alain__> I already ruled out any issue with cables and switch
<montjoie> no more info in dmesg ?
<alain__> [ 5.897745] libphy: 1c30000.ethernet: probed [ 5.981602] Generic PHY 1c30000.ethernet:01: attached PHY driver [Generic PHY] (mii_bus:phy_addr=1c30000.ethernet:01, irq=-1) [ 5.981620] sun8i-emac 1c30000.ethernet: device MAC address slot 0 02:20:53:2a:71:92
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<Pe3ucTop> Do anyone know difference between serial 16550A and U6_16550A
<montjoie> sorry alain__ didnt have any idea
<KotCzarny> maybe this patch helps. Pe3ucTop ^
<alain__> montjoie: no worries, not a big issue for me, HD works well enough. Was more to report the issue also so that someone else looking in the IRC log sees s/he's not alone.
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<Pe3ucTop> KotCzarny: thanks, I'll get a look. Any help is preferable :)
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<apritzel> Pe3ucTop: maybe the Linux serial driver limits the baudrate?
<apritzel> Pe3ucTop: I remember the 16550 being horrible in this regard in the past
<apritzel> Pe3ucTop: and you should not change the clock on yourself
<apritzel> that's not how it's supposed to work
<apritzel> technically the apb1 clock on the A13 can be derived from a much higher clock, so you should be able to get a much higher baudrate
<Pe3ucTop> apritzel: currently I'm trying to understand how to initialize clocks by kernel (not u-boot), I already tried change APB1 , got succes with changing clock source from OSC24 to PLL6
<Pe3ucTop> but not setting up frequency, when I tried to set APB1 200MHZ (by DTS) , I got Divide by 0 at kernel initialisation..
<apritzel> but that's a hack, actually the CCF should work that out for you
<apritzel> the CCF knows about the possible parents
<apritzel> note to self: never change the baudrate of the serial line you are connected to ;-)
<KotCzarny> :>
<Pe3ucTop> What I see - uBoot inilialize dividers and multipliers, and those are used for CCF ..
<KotCzarny> ...without opening screen session and a safeguard cmd line ;)
<Pe3ucTop> and I'm afraid APB1 clock could be changed after peripherial driver initialisation .. (UART/I2C/...)
<apritzel> Pe3ucTop: have you checked /sys/kernel/debug/clk/clk_summary
<Pe3ucTop> mm, not... Checking it right now..
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<apritzel> but indeed it doesn't work, my hunch is still that the serial driver is not asking for the right frequency in the first place
<apritzel> you can hack it with devmem2 though
<apritzel> just to prove that it actually works
<apritzel> what baudrate do you actually want?
<Pe3ucTop> going to reboot to check how it will show change of APB1 clock source ..
<apritzel> Pe3ucTop: devmem2 0x1c20058 0x1000018
<apritzel> but please check the data and no guarantees
<apritzel> that should set APB1 to 48 MHz
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<Pe3ucTop> ok, will check, currently have 600Mhz
<Pe3ucTop> It's strange , in doc is written that PLL6 is 1.2Ghz , in clock tree I see PLL6_Other 600Mhz
<apritzel> Pe3ucTop: well, the manual recommends 1.2 GHz, but as the clocks is programmable, the CCF can set up anything it wants
<apritzel> so what baudrate you want? 3Mbps?
<Pe3ucTop> 12.5M
<apritzel> so it's 0x1000002 then
<apritzel> (600 MHz / (2 + 1))
<Pe3ucTop> aha... but, sorry , which package is responsible for devmem2 ?
<apritzel> for APB2 at 200 MHz, divided by 16 = 12.5 MHz
<apritzel> Pe3ucTop: none, I guess
<Pe3ucTop> where to get sources ?
<apritzel> Google should point you to some free-electrons server
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<Pe3ucTop> yes, already looking for it..
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<apritzel> Pe3ucTop: but be warned: that changes APB1, which affects all UARTs and I2C
<apritzel> and nobody but you knows about it, I guess, so the serial driver thinks it's still at (24 / 16) MHz
<Pe3ucTop> yes, I know :) Thanks for pointing me for good tools, I'm still looking for correct way to initialise clocks.. and on 600Mhz / 37.5Mbps base rate, uart do not work stable as well UART do not work higher than 2.nnMbps , I tried with minicom (check by oscilloscope) :(
<Pe3ucTop> It's looks like many things need be done.. as well clk-sunxi / serial patching...
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<apritzel> Pe3ucTop: well, I am not really surprised, as the whole circuitry is not really designed for such high speeds, I guess
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<tkaiser> apritzel: Now I'm really curious, just confirmed that the same type of eMMC is also used on (my) BPi M2+ and results when tested a few months ago looked way better than yours now: https://forum.armbian.com/index.php/topic/990-testers-wanted-sd-card-performance/page-2#entry9886
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<apritzel> tkaiser: write: No space left on device; iozone: interrupted
<apritzel> so have to restart ...
<tkaiser> apritzel: Ouch
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<apritzel> tkaiser: well, it was a separate partition, but only 1.9GiB or so
<apritzel> tkaiser: how long does it take?
<tkaiser> apritzel: Better use the 2nd call since a lot faster due to just 100 MB test size. Approx 5 minutes.
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<apritzel> going into the 180 pages of SKHynix' "DDR3 SDRAM Device Operation" meanwhile ;-)
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<apritzel> tkaiser: waiting for a rerun of the first command, which number from the second command are you particularly interested in?
<tkaiser> apritzel: Hard to say. I'm currently re-testing with 4.9 on BPi M2+ too and results vary. In case you can spend the 5 minutes then the whole output from the following would be great: iozone -e -I -a -s 100M -r 4k -r 16k -r 512k -r 1024k -r 16384k -i 0 -i 1 -i 2
<tkaiser> apritzel: My tests now with 4.9 on BPi M2+: http://pastebin.com/7Jgv9dAK (strange since when testing with legacy kernel sequential write speeds exceeded 6 MB/s)
<apritzel> tkaiser: http://pastebin.com/h65WD52J
<tkaiser> apritzel: Thanks. Which fs? Ext4?
<apritzel> yes
<tkaiser> ok, I just realized that I'm testing with btrfs now :)
<apritzel> ;-)
<apritzel> maybe my fstrim before makes a difference on the write speed?
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<tkaiser> No idea. Btrfs should also try to use trim AFAIK: /dev/mmcblk2p2 / btrfs rw,noatime,nodiratime,ssd,space_cache,subvolid=5,subvol=/ 0 0
<tkaiser> Anyway: Results look better than expected for whatever reasons :)
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<tkaiser> Especially random IO
<apritzel> with the large blocksize: KB: 1843200, reclen: 4, write: 6394, read: 177429, random read: 138265, random write: 953
<apritzel> tkaiser: btw: do you know of a halfway sensible benchmark which is sensitive to DRAM speed?
<tkaiser> apritzel: Ok, benchmark is broken. The read values are BS anyway :)
<apritzel> tkaiser: indeed, was thinking the same ;-)
<tkaiser> apritzel: Just the opposite. At least sysbench --cpu is not affected by DRAM speed at all ;)
<tkaiser> I would use ssvb's tinymembench
<apritzel> no wonder since this is driven by supercomputer class SoC!!!1!!1!
<tkaiser> apritzel: Ah, cpuminer depends on DRAM speed
<apritzel> tkaiser: thanks, as usual ssvb's stuff looks good
<apritzel> tested the temperature sensor output yesterday with cpuburn-a53 ;-)
<apritzel> and tricked my wife into doing the finger test: how long can you stand cpuburn-a53 with your finger on the SoC? ;-)
<tkaiser> apritzel: Mean :)
<tkaiser> Just as an indication that there are benchmarks that benefit from higher memory bandwidth.
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<amw2320> Hi all, I'm trying to figure out how to get UART working on the dragontouch X10 and wanted to check if any had experience with this. I put together a device page for it here: https://linux-sunxi.org/TabletExpress_DragonTouchX10. I've followed the wiki guidelines, but have not been able to get output out of any pads on the chip. I've posted pictures of the front and back of the PCB board. Is there any way to check if somehow t
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<amw2320> Anyone know how the sys_config.fex file is read. Is this a file that is read directly if I edit it, or is it similar to a kernel config file that is used to configure uboot?
<Ixnus> Hello amw2320:
<amw2320> Hi Ixnus
<Ixnus> well done.
<Ixnus> interesting device A83T :)
<amw2320> It is. Not a lot out there yet it seems, so I'm fumbling around a bit
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<Ixnus> Jean-Francois Moine , Vishnu Patekar and wens: have it
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<amw2320> I have tried with the microSD breakout with no luck. I had to change around some settings to match the pin output of the A83T, but that seemed pretty straightforward.
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<amw2320> When that didn't work I disassembled the board to see if I could find another pin. I have read that UART can be disabled in some builds which is why I was concerned I am wasting my time unless I can confirm that UART is not disabled.
<Ixnus> I guess you can't get the board schematic ?
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