Turl changed the topic of #linux-sunxi to: Allwinner/sunxi /development discussion - did you try looking at our wiki? https://linux-sunxi.org - Don't ask to ask. Just ask and wait! - https://github.com/linux-sunxi/ - Logs at http://irclog.whitequark.org/linux-sunxi
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<a1d3s> good morning
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<KotCzarny> likewise: btrfs + snapshots?
<KotCzarny> or any other fs with that feature
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<igraltist> on long term compiling my orangipi-pc got hot to 75°C
<igraltist> i think i have to put some cooling stuff
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<scelestic> igraltist: with a heatsink?
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<igraltist> yes this i need
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<a1d3s> wow i got the damn bpi-m2-ultra to boot http://pastebin.com/HAdX2Zmw
<a1d3s> but it didnt find the root partition right
<igraltist> lol with tor can't access
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<igraltist> i should build a map which provider blocking tor
<beeble> a1d3s: check the polarity of your CD gpio
<a1d3s> beeble for the first try i only used the m2-plus dts , i know them is wrong for ultra
<a1d3s> but some things work :)
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<beeble> in that case the mmc controller doesn't match in more than the CD section :)
<a1d3s> i found in sinovoip bsp tree cd-gpios = <&pio PF 6 0 1 2 0>; and in mainline plus: cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
<a1d3s> what to do with 0 1 2 0 ?
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<MoeIcenowy> I really got a sample of the V3s-based Lichee Pi Zero
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<beeble> a1d3s: mux, pu/pd, drive, output level
<beeble> iirc
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<MoeIcenowy> V3s's SoC ID is 0x1681, only one more than H3
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<a1d3s> beeble: http://pastebin.com/9ttNE4t5 it looks better . not good :)
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<beeble> a1d3s: take a look at your mmc0 pin definition. could it be that it is set to xxx_NO_PULL? if if so try it with xxx_PULL_UP
<a1d3s> mmc0_pins_a: mmc0@0 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; mmc0_cd_pin: mmc0_cd_pin@0 { allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
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<wens> mmc0_pins_a should be PULL_UP
<a1d3s> wens ok will try
<a1d3s> and cd_pin NO_PULL?
<a1d3s> or both up?
<beeble> depends on the hardware. keep it PU since it seems to work now
<a1d3s> i'm not a programmer , all i do is try and error :)
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<a1d3s> wens your u-boot works , but why it is only 1GB Dram?
<wens> known issue
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<a1d3s> ok i thought i did something wrong :)
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<MoeIcenowy> wens: I got an Allwinner V3s board now
<MoeIcenowy> how can I port U-Boot to it?
<jelle> allwinner v3?
<KotCzarny> cheapo one core, dual cam soc
<jelle> all allwinners are cheap :D
<wens> MoeIcenowy: figure out dram :/
<MoeIcenowy> oh libdram...
<MoeIcenowy> the disaster
<jelle> oh action cam stuff
<a1d3s> the PULL_UP for mmc0 changed nothing .. sunxi-mmc 1c11000.mmc: smc 2 err, cmd 18, RD EBE !! <- this error is from eMMC (mmc2)
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<beeble> a1d3s: does your board have emmc? if so then enable PU there too
<a1d3s> beeble yes it have 8GB
<wens> a1d3s: add pull_up for it as well?
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<a1d3s> i pushed it to git
<wens> to be honest i haven't spent much time on the r40, other than adding u-boot support for it
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<MoeIcenowy> wens: should I port U-Boot first, or should I port Linux first, to a new SoC?
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<beeble> a1d3s: i hope you fixed your conflicts in the dts. otherwise it will not build and you are still using the old one
<wens> MoeIcenowy: depends on if you have something to boot it or not :p
<a1d3s> beeble the pi starts but very slow and hangs around on systemd
<wens> though having u-boot makes it much more interesting for others
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<beeble> you have some more unresolved conflichts in the file
<a1d3s> beele yes i have fixed this
<beeble> ok, just wanted to be sure that you are not using old files
<a1d3s> thanks :)
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<a1d3s> this was the latest commit
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<beeble> looks fine otherwise. you could try to change the bus width to 4 as a workaround if it's a timing issue
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<premoboss> hi, i have NANOPI NEO, OS armbian 5.20, linux 3.4.112. in can connect via ethernet cross cable (Static ip). if i use minicom, i see on PC the uboot messages, kernel messages, and login prompt but i canot login (usb/rs232 csable works good with other boards). but mi BIG probblme is rhgat i cannot user usb0 from pc to NEO, so i enter via eth0 and do modprobe g_ether and usb0 go up (i placed auto usb0; iface usb0 inet static, address 192.168.10.1; net
<premoboss> mask 255.255.255.0 into /etc/network/interfaces of NEO). so on NEO usb0 is up but it dont make usb0 pf PC going up. cable is ok and PC confioguration is ok (it works woth other embedded linux board). what is frong? maybe some config of Armbian? i ask help.
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<MoeIcenowy> wens, jemk: I remember you mentioned there's related documents about mctl?
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<wens> MoeIcenowy: imx6 reference manual
<MoeIcenowy> wens: thx
<MoeIcenowy> I think for V3s there's another way to initialize DRAM...
<MoeIcenowy> directly restore a register dump to the mctl regs
<a1d3s> beeble , some errors are gone with bus width 4 http://pastebin.com/vYDNTEFY but the device is damn slow
<NiteHawk> MoeIcenowy: V3s pull request done - I'll now rebase the H3/SID fix on top of that and also merge it, unless you have any objections
<MoeIcenowy> nitehawk: thx ;-)
<a1d3s> my old 286er is faster :)
<beeble> it brings only one core up. but even with that it shouln't feel that slow
<beeble> and there could be a clocking issue
<beeble> do you get a shell?
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<a1d3s> i'll try without systemd/udev if it runs faster an a login comes up
<a1d3s> the image is a minimal debootstraped jessie with kernel 4.9
<a1d3s> maybe i forgot some modules , didnt know :)
<MoeIcenowy> wens: In which situation will the controller returns "DRAM: 0 MiB" ?
<beeble> a1d3s: modules shouldn't matter for clockspeed. you can add init=/bin/sh to your kernel cmdline to just get a prompt
<beeble> and mybe look into sysfs cpufreq stats
<KotCzarny> MoeIcenowy: misdetection most likely
<KotCzarny> ie. wrong code
<MoeIcenowy> KotCzarny: I know that it's misdetection ;-)
<KotCzarny> ;)
<a1d3s> beeble do i need to rewrite https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/include/dt-bindings/clock/sun8i-h3-ccu.h?id=refs/tags/v4.9 one for r40? and what there the magic numbers :)
<wens> yes you will likely need a new driver for both the ccu and pinctrl for r40
<a1d3s> arg :/
<a1d3s> ok this is a thing for tomorrow
<a1d3s> now i will go home
<a1d3s> thx beeble and wens
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<MoeIcenowy> could anyone help me to analysis V3s's DRAM controller dump?
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<NiteHawk> wens: did you by any chance find an opportunity to verify the SID quirk (observed on H3) for A80?
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<MoeIcenowy> https://pastebin.anthonos.org/view/139b2e6e here's a dump of V3s DRAM controller registers under BSP U-Boot
<MoeIcenowy> who can help me to check it?
<jemk> i
<MoeIcenowy> jemk: thx!
<MoeIcenowy> what basic knowledge is needed to write DRAM controller drivers?
<jemk> looks a lot like h3, same zq quirk
<MoeIcenowy> but directly with H3 code path do not work
<MoeIcenowy> (the DRAM integrated is DDR2 according to BSP boot log
<jemk> oh, ddr2 isn't supported yet, it will be quite a bit different
<MoeIcenowy> what will be needed to add ddr2 support?
<beeble> for example ddr2 doesn't have zq calibration at all :)
<jemk> different timings, initialisation, some mode registers maybe
<MoeIcenowy> can I just use the register dump to initialize it?
<beeble> unlikely
<beeble> there are init sequences
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<jemk> no, the initialisation sequences have to be run correctly
<jemk> ... beeble is faster in typing ;)
<beeble> jemk: i cheat with shorter sentences :)
<KotCzarny> can it just work by register dump restore?
<jemk> the most important change would be MCTL_CR_DDR2 in mctl_set_cr i think
<wens> NiteHawk: no difference reading directly or through registers (i assume sid-registers forces this?)
<wens> NiteHawk: tested with sunxi-fel
<jemk> MoeIcenowy: two problems with this code, license and it isn't correct either
<MoeIcenowy> isn't correct either?!
<jemk> it doesn't have the zq calibration quirk and only sets fixed timings
<beeble> jemk: ddr2 doesn't have a zq calibration, thats a ddr3 feature
<wens> nice to have a hardware engineer here :)
<jemk> beeble: only the dram chips donthe controller can still do it, and the boot0 dump looks like it does
<jemk> *don't have it*
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<MoeIcenowy> by changing DDR3 to DDR2 in dram_sun8i_h3.c it still didn't work for V3s
<MoeIcenowy> or maybe we should also write fixed timings?
<wens> mainline u-boot doesn't support ddr2
<beeble> jemk: ah, i see. mctl does have zq calibration for ddr2. would probably work without too
<MoeIcenowy> wens: yes it's now the problem
<beeble> as long as you try different drive strenghts. but yeah, zq calibration for writes can help a lot
<MoeIcenowy> we got a chip which has only ddr2
<jemk> MoeIcenowy: there are more things of course, for example the dram mode registers, but they can be copied from the dump for now
<jemk> beeble: the zq cal isn't very good on sunxi anyway, so fixed values might be ok as well
<jemk> but you have to set the driver and odt strengths
<NiteHawk> wens: thx! yes, "sid-registers" would enforce the workaround method of reading via register - would only make a difference if the first "sunxi-fel sid" (memory access) would not yield the expected result
<jemk> MoeIcenowy: i usually add a register dump to u-boot and diff it with boot0 dump, then fix the differences one after another
<MoeIcenowy> could I create a dedicated driver for V3s which uses the BSP values to run the init process?
<MoeIcenowy> I think for V3s we have less situations
<MoeIcenowy> as all the DRAM wafers are the same
<jemk> hard-coded modifying the h3 code should be faster
<MoeIcenowy> ok
<MoeIcenowy> which part is most important? DRAMCTL0 (started at 0x01c63000)?
<jemk> yes, and 0x01c62000
<jemk> did you set a low enough dram clock, i don't think it can do 672mhz
<MoeIcenowy> I set 360
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<MoeIcenowy> mctl_channel_init function will return with error...
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<jemk> MoeIcenowy: try this http://sprunge.us/fSVH i changed what i noticed from your boot0 dump, the remaining stuff could then be diffed with the dump you get from u-boot
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<MoeIcenowy> jemk: got 32MiB!
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<KotCzarny> :)
<MoeIcenowy> oh it's because some my silly changes
<MoeIcenowy> just use your patch can give me 64 MiB
<MoeIcenowy> it seems that it didn't perfectly went back to main U-Boot...
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<MoeIcenowy> oh forgot to add the first V3s SID on the wiki
<MoeIcenowy> NiteHawk: it seems that V3s FEL boot met some problem...
<MoeIcenowy> after executing SPL, it can go back to FEL, and sunxi-fel {sid,ver} works
<MoeIcenowy> however, it didn't allow to execute SPL again...
<MoeIcenowy> (For my former SoCs, this time SPL can be executed again
<MoeIcenowy> and fail with usb_bulk_send error
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<jemk> MoeIcenowy: can you paste the register dump from u-boot?
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<NiteHawk> MoeIcenowy: are you using the BSP SPL? I think I have observed similar behaviour on other SoCs with BSP vs. mainline U-Boot, this phenomenon is not entirely unknown
<MoeIcenowy> NiteHawk: I'm using my homebrew SPL
<MoeIcenowy> jemk: still cannot run the main U-Boot
<jemk> the spl should dump the regs too with my patch
<MoeIcenowy> yes
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<MoeIcenowy> but I removed the message now
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<NiteHawk> MoeIcenowy: Maybe I'm just remembering stuff like https://www.mail-archive.com/linux-sunxi@googlegroups.com/msg12720.html incorrectly - but as I said: other have encountered similar problems before. obviously I can't tell if it's related to your specific SPL flavor, or some SoC-specific behaviour
<MoeIcenowy> or maybe just I clocked the CPU core too high
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<jemk> thx, looks like there is a bit more to do
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<MoeIcenowy> yes...
<jernej> MoeIcenowy: Does A64 U-Boot work if it is loaded through FEL?
<MoeIcenowy> the DRAM content is in a mess
<MoeIcenowy> jernej: the U-Boot itself works...
<MoeIcenowy> but I still cannot get graphics work
<jernej> that's I will try to fix tonight :)
<jernej> so, which file? u-boot-dtb.bin?
<jernej> oh, sorry, nonstandard cable needed for FEL, I guess it will have to wait until I receive proper cable
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<MoeIcenowy> jemk: I found what I writes to DRAM is not equal to what I read
<MoeIcenowy> is it because the DRAM controller is not fully correctly populated?
<jemk> MoeIcenowy: possible, i would have the next iteration to test ready: http://sprunge.us/OSTC
<jemk> there are some strange things with the bus-width
<jemk> it only has 16 bit, but in mctl_cr it is set to 32 bit
<MoeIcenowy> oh... 0x4a000000 seems to be beyond 64MiB DRAM...
<jemk> how much ram does it really have btw?
<MoeIcenowy> 64MiB .
<MoeIcenowy> the usual loading address of our mainline u-boot is 0x4a000000...
<MoeIcenowy> jemk: why do you comment out mctl_set_master_priority?
<jemk> because boot0 doesn't set it, i just try to do what boot0 does
<jemk> we can later think about what this means, first it just has to work
<jemk> found another mistake, we need bank detection, your ddr2 only has 4 banks, you should change to MCTL_CR_FOUR_BANKS in mctl_set_cr before trying
<MoeIcenowy> at that time I got 32 MiB ...
<jemk> you can't trust this output anymore, it doesn't take number of banks into account
<MoeIcenowy> and the displayed size become 32MiB
<jemk> but now the phy stuff looks correct, so after fixing size detect it should work
<MoeIcenowy> how to fix size detect?
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<jemk> i hope adding a bank detection is enough
<MoeIcenowy> but we hardcoded it to 4 banks...
<jemk> and the detection still assumes there are 8
<MoeIcenowy> I cannot understand this...
<MoeIcenowy> is there other things that could be forgot to be doubled?
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<KotCzarny> i think wens had similar trouble with a80
<Ntemis> hey guys does H3 support uEnv.txt ?
<KotCzarny> h3 doesnt
<KotCzarny> uboot does
<MoeIcenowy> KotCzarny: he's R40
<MoeIcenowy> which met the trouble
<KotCzarny> MoeIcenowy: maybe, dont remember exactly
<Ntemis> KotCzarny: so not possible?
<KotCzarny> ntemis: so your question wasnt exactly on point
<KotCzarny> its up to uboot, not soc
<Ntemis> oh i see
<KotCzarny> if you use legacy uboot, no, if you use mainline uboot, yes
<Ntemis> ah great thanks
<KotCzarny> also, how is your 800mhz? did you confirm its snake oil or real thing?
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<MoeIcenowy> jemk: another problem
<MoeIcenowy> I hacked the loading address of u-boot to 0x41000000 and entered U-Boot main binary
<MoeIcenowy> but it stucks at "DRAM: 0 Bytes"
<jemk> one step after another, first we need a matching register dump, then we are pretty sure dram is initialised correctly
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<MoeIcenowy> I think the DRAM is in fact 32bit...
<MoeIcenowy> yes, it's why it is reported as 32 MB
<MoeIcenowy> oh your 2nd patch fixed this
<beeble> MoeIcenowy: a partnumber could clarify that
<MoeIcenowy> beeble: it's a in-package die
<MoeIcenowy> no partnumber
<MoeIcenowy> or I should say the DRAM's partnumber is just "Allwinner V3s"
<beeble> ah, multi die package. i see.
<jemk> there are only two data byte lanes in the phy, so only 16 bit
<MoeIcenowy> but according to BSP cr register, it's 32-bit
<MoeIcenowy> and with 32-bit settings at least U-Boot is not corrupted
<jemk> maybe this bit means full and half buswidth instead of 32 and 16, then it would fit
<jemk> i don't think we ever found a name anywhere
<MoeIcenowy> yes...
<beeble> ah, so it's a V3s
<MoeIcenowy> how can I detect whether DRAM is stable?
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<beeble> uboot has a memtester command. good for a first try
<MoeIcenowy> but I haven't entered U-Boot...
<beeble> ok, so still in spl i see
<beeble> then write to dram adresses and read back
<beeble> if it's the same you have a good chance that you are doing something right
<beeble> everything is moving on this new allwinner website. my head is spinning
<jemk> MoeIcenowy: bank detection: http://sprunge.us/gAHP
<jemk> if i didn't miss anything and the detection is correct this should now produce a 1:1 boot0 identical dump (except some volatile status registers)
<jemk> ah, its on top of the last patch now...
<MoeIcenowy> should the bank detection be in H3?
<jemk> if it works we should enable it everywhere where ddr2 could happen
<MoeIcenowy> or we should only keep it for V3s?
<MoeIcenowy> I think finally all the code should be #ifdef CONFIG_MACH_SUN8I_H3_DDR2, right?
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<jemk> all the stuff i did now needs massive cleanup if it works, too many things just hardcoded now
<MoeIcenowy> but many things are replacing one hardcode with another hardcode ;-)
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<jemk> can you paste a (hopefully last for now) dump with this patch, if everything fits cleanup can start
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<MoeIcenowy> jemk: ^
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<jemk> perfect, looks like boot0, so dram should work from the hardware point of view
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<MoeIcenowy> you may want to rename the ifdefs, right? ;-)
<jemk> since thats more ddr2 specific than v3 specific, yes
<MoeIcenowy> but the U-Boot payload still argues with "0 Bytes DRAM"...
<MoeIcenowy> (Even if itself lies in DRAM
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<jemk> i have never looked into the u-boot part, no idea how their dram size detect works, it just worked for me
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<jernej> MoeIcenowy: Are you aware that you for some reason commented out enabling DE2 gate here: https://github.com/Icenowy/u-boot-1/commit/1e860de9f0f33c3228e1d0fa725365aa3a019638#diff-6096d3b4220e70859510b8f0adf51cd4L359
<MoeIcenowy> jernej: it's only some left testing code. You can just uncomment it, and it won't work :-(
<jernej> as I said, I will wait until A to A USB cable comes
<KotCzarny> make one yourself from 2 old mice?
<jernej> but please try this: uncomment above mentioned line and replace "clrbits_le32(SUN8I_DE_SEL_REG, 1);" with "setbits_le32(SUN8I_DE_SEL_REG, 1);"
<KotCzarny> or two old printer cables
<jernej> well, there is a box with cut cables at my work, but I'm on vacation till 9th...
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<MoeIcenowy> got the reason for U-Boot's "0Bytes DRAM"
<MoeIcenowy> U-Boot reserved 64MB for malloc
<MoeIcenowy> but the board have only 64MB
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<KotCzarny> lol
<KotCzarny> such a kidder
<MoeIcenowy> not U-Boot reserved 64MB
<MoeIcenowy> it's sunxi-common.h configs to reserve 64MB
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<NiteHawk> malloc(the_world) :D
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<MoeIcenowy> ok it seems like some romantic sentence
<MoeIcenowy> give(you, malloc(the_whole_world)) ;-)
<MoeIcenowy> although I think we the mainline developer have never thought the situation that we have only 64MiB as the whole world ;-)
<NiteHawk> hey, 640K ought to be enough for everyone
<beeble> fyi: a large ubifs can require a lot of malloc size during recovery
<beeble> large >= 2GB
<MoeIcenowy> something to mention: the official system firmware media of V3s is... SPI NOR flash
<NiteHawk> interesting. so the lichee has an spi flash onboard?
<KotCzarny> how much?
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<MoeIcenowy> I don't know how much either...
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<MoeIcenowy> my board is a very early sample, that needs a wire to solve the power problem ;-)
<MoeIcenowy> NiteHawk: yes, and the SPI flash is intended to be one of the main storages
<KotCzarny> MoeIcenowy: does it come with any os?
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<jonkerj_> I've ordered a opi one, to enhance my development rig. Cannot wait to show the result off :-)
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<jonkerj> it will replace the usb-uarts, and the usb-part in the usb-relay
<jonkerj> also, a 5-port ethernet switch which can be powered from my 5v brick
<jonkerj> so it will connect to mains and to some ethernet port, and offerrs remote UART and powercycle for my h3 boards
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<KotCzarny> make a howto on your user page
<KotCzarny> with pics
<KotCzarny> :)
<jonkerj> of course
<jonkerj> that will be half of the fun
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<nikre> is the gpio order different in opi one and pc?
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