<smkz>
I was debugging a board with one of those tiny 1.8V switching regulators (forgot the part number, wasn't my board) and I had to unsolder it and 1) the package broke apart (which was fine; the regulator was suspected bad anyway 'cause the 1V8 line was at zero volts) and 2) a day later I found a part of the regulator I'd removed *in another room*, in my *bed*
<qu1j0t3>
ruh roh
<qu1j0t3>
do you have cats
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<azonenberg>
lol
<azonenberg>
how did it break apart?
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<smkz>
it had a built-in inductor and the inductor core material somehow got unbonded from the rest of the package (and likely got stuck on my clothes or something)
<azonenberg>
Lol interesting chip
<azonenberg>
my only problem with most of those parts is that they can't supply enough current for a big beefy fpga design
<azonenberg>
Lately my mainstay for small to medium sized projects has been the LTC3374
<azonenberg>
i've done at least two designs with it recently that i recall
<azonenberg>
Four phases, eight outputs (two per phase)
<azonenberg>
1A per output
<azonenberg>
You can parallel up to four of the eight outputs for increased current
<azonenberg>
My only complaint is that it maxes out at 5.5V input so you can't use it for 12V designs
<azonenberg>
But it works great for a vcore + several vio rails
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<azonenberg>
digshadow, mithro, others involved: fun question
<azonenberg>
most (if not all) of my 7 series bitstreams include a write to register 0x13
<azonenberg>
one word of 0x00000000
<azonenberg>
This is a reserved register i can't see mentioned anywhere in table 5-23 of UG470
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<azonenberg>
Any guesses of what it does? Anybody tried fuzzing it to see what other bit values do?
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<Morn_>
hallo wie markiere ich die afra als offen? :D
<Morn_>
sorry wrong channel
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<kc8apf>
azonenberg: I've noticed that too. I haven't tried fuzzing it yet. I've mostly figured out one undocumented bit in CTL1 related to how frame addresses are autoincremented.
<azonenberg>
oh that's cool
<azonenberg>
did you doc that anywhere?
<azonenberg>
whats weird is, its only set in vivado bitstreams afaik
<azonenberg>
My original code written for crunching ISE bitstreams threw an assertion when i first gave it a vivado .bit lol
<kc8apf>
writing proper docs for all I've learned about the low-level bitstream operations is close to the top of my TODO list
<azonenberg>
ah cool
<azonenberg>
also, the online html docs for kintex show interconnect for the bram tiles
<azonenberg>
but i cant find init data
<azonenberg>
is bram init data stored separately? like, in different address ranges?
<kc8apf>
we haven't finished init yet
<azonenberg>
i meant i dont even see a big blob of unknown bits
<kc8apf>
yes, different config block type
<kc8apf>
which means completely different part of the frame address space
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<digshadow>
azonenberg: hmm kc8apf would be better to ask that
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<azonenberg>
kc8apf: oh, ok that makes sense
<azonenberg>
i was confused because i expected to either see known data, or a big unknown blob
<azonenberg>
that while we may not know the bit ordering is "obviously" ram init data of some sort
<azonenberg>
is anyone looking at bram/dsp tiles on artix vs kintex? its not in the html db yet but that doesnt mean a ton :p
<azonenberg>
i'm quite curious how similar artix vs kintex logic fabric is
<azonenberg>
my guess: same slice / ram / dsp primitive RTL, different layout optimized for performance vs area
<azonenberg>
and possibly kintex has more routing channels for reduced congestion and higher fmax
<pie_>
y'all working on bitstreams? :3
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<kc8apf>
azonenberg: HTML gets generated for a region of interest that is a range of frame addresses. It was expanded to include a BRAM segment but only in the CLB_IO_CLK block type portion of the address space. I haven't look at what needs to be done to support a non-contiguous region of interest.
<kc8apf>
from my reading in the various UGs, all 7-series parts share common tile structures and clock region layout.
<kc8apf>
so far we know CLBs are layed out exactly the same.
<kc8apf>
pie_: yup. we've got a few examples of generating them for CLBs without Vivado. Requires hand-writing configuration details right now. Looking into how to convert from VPR output to our format to get Verilog->bitstream.
<kc8apf>
pie_: we also know how to read the bitstream enough to create our syntax from existing bitstreams.
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<kc8apf>
azonenberg: so far it looks like "rows" in the frame address are very regular with 2-3 variations. I expect kintex uses the same "row" structures as artix and just has more of them.
<pie_>
(fancy)
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<azonenberg_work>
pie_: of course we are, bitstreams are fun
<azonenberg_work>
I'm not actively working on the x-ray stuff but following it fairly closely
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<rqou>
O_o the ohio e-waste recycler that was selling voting machines just recently switched to free shipping