<gruetzkopf> that'd be great (especially as i have like 50m of those in 40x40 around)
<rqou> also, as i've complained about before, a hotplate stirrer? https://www.youtube.com/watch?v=a3RWe-EZ9UQ
<q3k> when it comes to diy lab gear, i highly recommend making your own centrifuge for eppie tubes
<q3k> absolutely terifying
<q3k> especially if you try to 3dpring the spinamathinging part
<q3k> *3dprint
<rqou> i don't currently have a need for a centrifuge
<q3k> neither did i, but it was fun to stuff samples in it and see what happens ¯\_(ツ)_/¯
<q3k> and yes, it is a hard drive ziptied to a brick
<Ultrasauce> that is definitely the most ghetto lab equipment i've ever seen
<q3k> i'll take that as a compliment :D
<qu1j0t3> q3k: that's brilliant
azonenberg_work has quit [Ping timeout: 240 seconds]
<sorear> found this on a website claiming to be affiliated with yosys. is it as fractally wrong as I think it is? > All the silicon manufacturing nowadays is in the hands of a few big companies which play their monopoly of lone capability of manufacturing microchips by charging around 20'000 USD per prototype and letting an engineer wait for months until he can test his design physically.
azonenberg_work has joined ##openfpga
* qu1j0t3 seizes the means of production to test the theory
<rqou> i'm not sure about the business side, but that cost sounds right
<sorear> rqou: what I'm saying is that if libresilicon.com has made radical improvements in stepper technology, they should lead with that, or at least mention steppers so I know it's a company and not a hacker news comment.
<sorear> because I'm pretty sure Intel does not get same-month service for eng samples from their own fab
<sorear> [OT here but seems to be a lot of people here who know shit from shinola about fab work]
<sorear> if they weren't claiming endorsement from yosys I'd ignore it completely.
<cr1901_modern> sorear: I took a microfab class 6 years ago. I didn't pay much attention to it. And the fact that it's completely out of my price range to do my own == little motivation to relearn
<sorear> cr1901_modern: that's not the point
<sorear> cr1901_modern: i'm asking for a second opionon on my assement that they're full of it
<sorear> cr1901_modern: if you haven't done fab-adjacent work you probably cannot provide one
<cr1901_modern> No I can't.
<q3k> sorear: libresilicon.com?
<sorear> yes
<q3k> sorear: i would have given them the benefit of the doubt, but then I saw 'thereum smart contracts track commercial usage of your designs and incentivize more FOS hardware development'
<q3k> which sounds like absolute bullshit
<sorear> that was the other thing that set off alarms
<azonenberg_work> Lol yes that raises red flags
<q3k> as far as I can tell they're trying to implement something akin to the osu018 process https://github.com/leviathanch/ls018
* azonenberg_work wonders how many people who create "smart contract" startups actually have litigated a contract in court
<q3k> at least looking at the standard cells they use
<q3k> but no idea if the chemistry/physics behind it makes any sense https://github.com/leviathanch/libresiliconprocess
RaivisR_ has joined ##openfpga
GenTooMan has joined ##openfpga
RaivisR__ has quit [Read error: Connection reset by peer]
<azonenberg_work> So they want to do their own fab in house?
<azonenberg_work> "suggestion: dry etching"
<azonenberg_work> This suggests nobody actually has fab experience
<azonenberg_work> 4: implant
<azonenberg_work> "grow oxide"
<azonenberg_work> as the only step
<azonenberg_work> And they stop at field oxide, they dont talk about BEOL at all
<rqou> yeah, it honestly looks like microfab homework :P
<rqou> azonenberg_work: we really need to do our hobby-friendly 5um/1um process
azonenberg_work has quit [Ping timeout: 248 seconds]
<Ultrasauce> nevermind just a boring marketing video, thought there'd be more process details
digshadow has quit [Ping timeout: 256 seconds]
azonenberg_work has joined ##openfpga
digshadow has joined ##openfpga
GenTooMan has quit [Quit: Leaving]
<gruetzkopf> i do have a centrifuge
<gruetzkopf> it's from the early fourties
<pie__> Ultrasauce, sucks when that happens :(
<pie__> so. anyone have any conspiracy theories about ITER?
<pie__> sucks how CERN gets all the love ;P
<awygle> does "it's a bad design" count as a conspiracy theory if i'm not a plasma physicist?
<Bike> well you gotta involve a conspiracy. like, it's a bad design because of deliberate sabotage by... CERN? north korea? reptilians? be creative
sgstair has quit [Remote host closed the connection]
<awygle> "it's a bad design that is politically expedient and therefore basically impossible to change"
sgstair has joined ##openfpga
<awygle> tokamaks are only the most advanced designs because they're what money has been spent on
Bike has quit [Quit: Lost terminal]
<awygle> my ignorance is as good as your knowledge
rohitksingh-demo has quit [Quit: Leaving.]
rohitksingh-demo has joined ##openfpga
nrossi has joined ##openfpga
<rqou> did you know, when you desolder a chip, the removed chip will be hot
<rqou> :P
* rqou adds another tally to the self-injury count
<awygle> Finger Scars: Collect All 10!
rohitksingh-demo has quit [Quit: Leaving.]
<rqou> well, this was one of the fingers that got nitrated the other day
<awygle> i am at 7, mostly from soldering irons, one from cookies, and one from flag football
<rqou> you make cookies?
<awygle> course
<awygle> cookies are delicious
<rqou> i've also made cookies, but then my ex-housemate took the mixer
<awygle> i make them less now that i can't just eat whatever i want whenever i want :(
<azonenberg> rqou: did your Fi(NO3) combust more readily?
<awygle> but i actually cook quite well
uovo has quit [Ping timeout: 265 seconds]
<rqou> azonenberg: no
DocScrutinizer05 has quit [Disconnected by services]
DocScrutinizer05 has joined ##openfpga
oeuf has joined ##openfpga
DocScrutinizer05 has quit [Disconnected by services]
DocScrutinizer05 has joined ##openfpga
<whitequark> cr1901_modern: yes, the idea that the default set of descriptors / protocol is the same as FTDI
<whitequark> except not as buggy
<rqou> presumably not tripping the clone check either>
<rqou> ?
<whitequark> no idea how their clone check works
<rqou> iirc it tries to write the the embedded eeprom at a misaligned address
<rqou> the real chip ignores it and the clone corrupts the eeprom
<rqou> the no-longer-bricks-your-chip driver then writes the original value back
<rqou> (yes, there is a race condition)
<whitequark> oh
<whitequark> but my eeprom layout doesn't match ftdi's
<whitequark> so i'll just ignore all writes
Morn_ has quit [Quit: ZNC - http://znc.in]
wolfspraul has quit [Read error: Connection reset by peer]
pie__ has quit [Ping timeout: 246 seconds]
DocScrutinizer05 has quit [Disconnected by services]
DocScrutinizer05 has joined ##openfpga
DocScrutinizer05 has quit [Disconnected by services]
pie_ has joined ##openfpga
DocScrutinizer05 has joined ##openfpga
m_t has joined ##openfpga
eduardo_ has joined ##openfpga
DocScrutinizer05 has quit [Disconnected by services]
DocScrutinizer05 has joined ##openfpga
DocScrutinizer05 has quit [Disconnected by services]
DocScrutinizer05 has joined ##openfpga
eduardo__ has quit [Ping timeout: 260 seconds]
DocScrutinizer05 has quit [Disconnected by services]
DocScrutinizer05 has joined ##openfpga
DocScrutinizer05 has quit [Disconnected by services]
DocScrutinizer05 has joined ##openfpga
DocScrutinizer05 has quit [Disconnected by services]
DocScrutinizer05 has joined ##openfpga
pie_ has quit [Ping timeout: 240 seconds]
rohitksingh-demo has joined ##openfpga
rohitksingh-demo has quit [Ping timeout: 240 seconds]
rohitksingh-demo has joined ##openfpga
rohitksingh-demo has quit [Client Quit]
<sorear> did something happen with ITER? or is that the point
pie_ has joined ##openfpga
<whitequark> sorear: ITER?
<whitequark> international thermonuclear experimental reactor?
<whitequark> rqou: awygle: i have... exactly one scar on my body, because i heal like a stray dog
<whitequark> (you could never tell it's a scar. actually i can't tell, i just know by the location)
<whitequark> guess what's it from
<sn00n> laser?
<whitequark> answer: I had an ADSL modem that worked so badly that I punched it. or more specifically, punched *through* it. unfortunately, it had one of those screw standoff features in its plastic cases, which are significantly more durable than the rest of the case
<q3k> huh.
<whitequark> I used to have very serious anger issues.
<sn00n> don't punch em, shoot em! (wearing safety glasses)
<whitequark> my previous laptop has made probably a dozen dents in various walls, not to mention that nearing the end of its life, the case became somewhat concave. impressively, the walls suffered more damage than the laptop
<sorear> whitequark: ya, <pie__> so. anyone have any conspiracy theories about ITER?
<whitequark> it actually survived something like four years of this relationship, and three replacement keyboards
<whitequark> modern electronics is absurdly sturdy
<q3k> depends on what you buy
<whitequark> that one was asus
<q3k> an el cheapo acer laptop from a supermarket probably won't even survive a fall onto a carpeted floor
<q3k> you'll be lucky if they don't burst into flames when you look at them funny
<whitequark> it was built like shit, the case creaked at the joints, the glue in it failed, the hinge died within like half a year, and screws popped through the stamped aluminium at the earliest opportunity
<whitequark> well not the hinge, the screws attaching the hinge to the display panel
<whitequark> I drilled six holes in the panel and put M2 screw in each, never gave me any trouble since
<sn00n> maybe you're simply not a great pitcher?
<whitequark> lol
pie__ has joined ##openfpga
pie_ has quit [Ping timeout: 256 seconds]
pie__ has quit [Ping timeout: 240 seconds]
<lain> has there been any progress in altera bitstream RE?
<lain> (I don't even know if anyone is working on that)
pie__ has joined ##openfpga
<sorear> I for one haven't heard of any
<m_t> lain, https://lse.epita.fr/lse-summer-week-2016/slides/lse-summer-week-2016-07-maxv_cpld.pdf . Haven't checked if they ever made any progress...
<lain> thx
<lain> I wonder if their format is documented like xilinx's
<lain> I have a bitstream file (.rbf) and I want to figure out specifically what device it targets
<lain> based on bitstream size (56,167,552 Mbit), it's either a Cyclone V E A7, V GX C7, or V GT D7
<lain> oh nvm, the original part number is right there
<lain> gg manufacturer for getting a custom laser marking and not changing the part number
<lain> member code A7, so it's a Cyclone V E A7 in 7 speed grade
digshadow has quit [Ping timeout: 240 seconds]
pie__ has quit [Ping timeout: 240 seconds]
user10032 has joined ##openfpga
mumptai has joined ##openfpga
azonenberg_work has quit [Ping timeout: 246 seconds]
digshadow has joined ##openfpga
<nurelin> lain: http://git.bfuser.eu/?p=marex/typhoon.git;a=summary ?
<lain> nurelin: interesting, thanks
<cr1901_modern> I wish openocd allowed one to upload a file from a remote computer. Guess I'm creating a netcat abomination to pipe a file in a loop...
<cr1901_modern> s/upload/jtag program/
<lain> I thought it worked with sockets?
<lain> (I don't really know, I just vaguely recall that it used sockets. haven't poked openocd in ages)
<cr1901_modern> It does, but:
<cr1901_modern> 2. Even if it didn't, I'd still have to place the file to be uploaded on the local machine manually
<cr1901_modern> 1. The telnet server binds to localhost
<cr1901_modern> (Context: Vivado is installed on a remote computer... I want to use my boards from my local computer)
<sorear> and apparently allows unauthenticated code execution from anything that can connect to the socket
<cr1901_modern> yea I saw that bug today too
<cr1901_modern> I think I'll "just" use pyftdlib and the on_file_received hook to invoke openocd
<cr1901_modern> telnet is just "netcat but control characters are special", right?
<sorear> if you consider FF to be a control character, then sure
<lain> you could use iMPACT
<lain> if you're doing xilinx devices
<lain> but their remote stuff is junk :<
<cr1901_modern> I didn't know it could do remote, but I'd like to avoid Xilinx tools as much as possible. I'm sure you understand.
pakesson has quit [Ping timeout: 264 seconds]
nrossi has quit [Quit: Connection closed for inactivity]
ZipCPU_ has joined ##openfpga
ZipCPU has quit [Ping timeout: 256 seconds]
ZipCPU_ is now known as ZipCPU
azonenberg_work has joined ##openfpga
azonenberg_work has quit [Client Quit]
azonenberg_work has joined ##openfpga
<rqou> yeah, iMPACT has a remote jtag protocol
<rqou> i keep meaning to email diamondm1n about it and keep forgetting
<rqou> tmbinc RE'd it
<lain> it's crap
Dolu has joined ##openfpga
<lain> wastes a ton of bandwidth, doesn't obey its own specs
<rqou> yeah, tmbinc mentioned it has some bug so his tool follows the state machine and ignores the broken state transitions
<rqou> for bonus fun, some _xilinx_ intern accidentally stole the code without proper attribution
<azonenberg_work> lol
<azonenberg_work> accidentally?
<rqou> presumably the intern couldn't even find the internal docs about the protocol
<azonenberg_work> I've been meaning to add support for impact remote jtag
<rqou> it was for some random appnote
<azonenberg_work> in libjtaghal
<azonenberg_work> I also want to redo the jtaghal protocol to use protobufs
<azonenberg_work> Now that i'm making a protobuf library for FPGAs i can do an embedded host for it
mumptai has quit [Quit: Verlassend]
user10032 has quit [Quit: Leaving]
Morn_ has joined ##openfpga
m_t has quit [Quit: Leaving]
Bike has joined ##openfpga
ZipCPU has quit [Ping timeout: 256 seconds]
ZipCPU has joined ##openfpga
rohitksingh-demo has joined ##openfpga