<rqou>
azonenberg_work: time to go all EH&S on me again? :P
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<azonenberg_work>
rqou: yes
<azonenberg_work>
I dont have to say it, you already know what i'm gonna say
<rqou>
hey, nitrile gloves don't work, and i didn't have the right type :P
<rqou>
i actually need to check what type of gloves is resistant to fuming nitric acid
<azonenberg_work>
Neoprene should work if its thick enouhg
<rqou>
apparently people normally recommend butyl rubber?
<pie_>
something that bothers me about gloves is like...you arent gonna throw em out after every use, so how do you know if some small amount of chemical hasnt leeched through it, which your hands are gonna soak in for a while
<pie_>
i mean like, you use your gloves for a bit,then put them away for a while and surface contamination leeches through
<qu1j0t3>
well that's the thing isn't it.
<qu1j0t3>
don't google HF accidents at all
<qu1j0t3>
or you'll never look at gloves the same way
<pie_>
well when dealing with stuff like HF you probably DO switch your gloves every time >_>
<qu1j0t3>
i wonder if one day we will have augmented gloves that actually have a breach alarm
<qu1j0t3>
self healing gloves
<rqou>
um, nitrile is resistant to HF
<rqou>
right?
<qu1j0t3>
well, some of the worst accidents were glove leaks...
<sorear>
qu1j0t3: before or after hobbyist-accessible telerobotics?
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* qu1j0t3
shrugs
<pie_>
hobbyist vr telerobotics
<pie_>
would be some cool shit
<qu1j0t3>
really good pantographs and manipulators for smd repair was something i vaguely thought might be nice
<qu1j0t3>
i suppose they exist
<rqou>
azonenberg_work: ok, i ordered some butyl rubber gloves, happy now?
<azonenberg_work>
Happier :p
<azonenberg_work>
pie_: this is why you wash and thoroughly decon gloves after use
<pie_>
oh ok
* pie_
sighs
<pie_>
i cant figure out why me dev env doesnt seem to be building/downloading/debugging my program....
<azonenberg_work>
pie_: if nothing else, putting away contaminated PPE means you're potentially exposed to whatever is on them while you remove and put them back on
<azonenberg_work>
same reason hazmat crews hose off after being in a scene
<pie_>
right
<azonenberg_work>
On the other hand disposable gloves, like exam gloves, you don't normally decon
<azonenberg_work>
you remove them carefully so that you never touch the outside of the glove
<pie_>
so it looks like its not even building the .o files for some reason!!?!?!?
<pie_>
azonenberg_work, right
<azonenberg_work>
Generally the process is to use one glove to pinch the outside of the other, pull that one off
<azonenberg_work>
turning it inside out as you do to keep contamination on the inside
<pie_>
i just figured nitric acid gloves wouldnt typically be the disposeable kind or something
<azonenberg_work>
then use a clean finger to slide inside the cuff of the other glove and again pull it off inside out
<pie_>
or the "less disposeable" kind
<azonenberg_work>
Generally for strong acids etc you'd use thicker gloves, yes
<azonenberg_work>
Which means deconning them after use matters
<pie_>
how do you decon the inside of the material though....
<azonenberg_work>
To prevent them from degrading in storage (almost any corrosive will EVENTUALLY burn through a glove if left on it for enough time) and to avoid contaminating the storage area / other lab users
<azonenberg_work>
You dont
<pie_>
i mean obviously presumably youd rather not get them contaminated in the first place :P
<azonenberg_work>
Once you remove the stuff on the outside, anything that diffused partway through the material should diffuse out the same way it came in
<azonenberg_work>
and eventually offgas etc
<pie_>
hm ok
<qu1j0t3>
azonenberg_work++
* qu1j0t3
always learns something in here
<rqou>
like my poor safety practices? :P
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<rqou>
whitequark: did you ever end up with nitrated orange fingers?
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* pie_
cries
<pie_>
i think its not running the linker
<pie_>
why isnt it running the linker
<pie_>
though at this point I've thought a lot of things
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<whitequark>
rqou: nope
<rqou>
whitequark you managed to get nitrations to go into thermal runaway but never ended up with orange fingers?
<whitequark>
not me!
<whitequark>
my roommate
<whitequark>
oh, wait, runaway
<whitequark>
not explosion
<whitequark>
yeah, sure, I actually stopped the runaway by running very quickly and placing a large bowl of water under it
<whitequark>
for some reason I react pretty well to emergencies like that
<rqou>
lol nice
<rqou>
did your roommate end up with orange fingers? :P
<whitequark>
not sure
<whitequark>
I wasn't there
<whitequark>
that's why it exploded
<rqou>
lol
<rqou>
you don't seem to have too much faith in your roommate
<whitequark>
she is extremely new to chemistry
<rqou>
i'm technically "pretty new" too
<rqou>
i've only done highly-supervised high-school-level labs before
<whitequark>
she didn't have chemistry in high school.
<whitequark>
at all.
<rqou>
ah, that level
<whitequark>
yes.
<rqou>
i definitely wouldn't want to do a nitration as a beginner
<whitequark>
I don't know why she di
<pie_>
she didnt know better
<pie_>
?
<pie_>
(I probably wouldn't know better but would end up reading enough to probably be sufficiently reluctant :P)
<pie_>
N is for explosion
<rqou>
pie_: try F
<pie_>
f is for face is melting?
<pie_>
hmm except no..
<rqou>
if F isn't enough, try FOOF :P
<pie_>
¯\_(ツ)_/¯
<pie_>
jesus christ that looks terrifying
<pie_>
somethign something peroxide, something something F
<rqou>
i think the only fluorine chemistry I would consider doing is using aqueous HF
<rqou>
but with better safety precautions than I've been demonstrating so far
<pie_>
comment says "I’d like to see N(N3)3 and octaazacubane made. "
<pie_>
>> octaazacubane
<whitequark>
...
<whitequark>
so you know the thing where you reassemble a device, have spare parts, but everything seems to work?
<rqou>
btw, if you want to play with some "safer" azides, you can try disassembling an airbag
<whitequark>
I just reimplemented a large chunk of FTDI's MPSSE with four times as few commands but just as much capabilities (or so it seems)
<rqou>
is this hdl or software? I've been meaning to do that but never got around to it
<whitequark>
hdl
<pie_>
if you can breathe on it and it still works i bet its totally fine
<rqou>
wait, you implemented usb as well?
<whitequark>
no
<whitequark>
CYP7C68013A
<whitequark>
erm, CY7C
<whitequark>
biology has corrupted me
<rqou>
wait, so it's software and an fpga combined?
<whitequark>
not really
<whitequark>
68013A serves as a very fat USB pipe
<whitequark>
(it can saturate 480 Mbps)
<rqou>
and the fpga implements mpsse?
<whitequark>
I want to make this a fairly general developer board that lets you push ungodly amounts of data into an iCE40 FPGA that in the default configuration works as a JTAG dongle
<whitequark>
yes
<whitequark>
or, really, anything you want
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<whitequark>
thanks though, the sdcc code will help
<whitequark>
my idea is specifically to avoid dealing with cy7c as much as possible and do everything on the FPGA
<rohitksingh-demo>
yeah, everything in fx2 itself...your approach to use fx2 + ice40 might be an improvmement
<rohitksingh-demo>
*improvement
<whitequark>
for example, I want to have fast UARTs that actually work reliably
<whitequark>
3 Mbps+
<whitequark>
none of the USB-UART chips do it...
<rohitksingh-demo>
yeah, ice40 + fx2 is the way to go then! iirc fx2 can just barely do 115200 in software
<whitequark>
yes.
<whitequark>
the 8051 in it is very slow.
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<rqou>
azonenberg: i think i asked you this before, but what's your favorite decap+uv "victim" chip?
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<sorear>
prjxray htmlgen is nondeterministic and puts sections in a different order each time it runs, worth filing a bug?
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<eduardo_>
whitequark: you could implement dynamic loading of bitstream from PC over FX2 into ice40 SRAM. So your FX2 plus ice40ultraplus board would be very flexble. It would just need support on the host side to do the bitstream loading.
<whitequark>
eduardo_: nah, I'll put a 2Mbit I2C flash onto it
<whitequark>
I mean, of course you could load the bitstream manually too if you want
<whitequark>
but the idea is that the baseline state of the board is "JTAG adapter that works with literally any software" and then you can tweak it
<whitequark>
it's extremely widely used for interfacing with FPGAs. like on most digilent boards without native USB capable transceivers in the FPGA I think?
<eduardo_>
whitequark: I suggest you to go for the ice40UP if the packaging and number of IOs is ok for you.
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<whitequark>
eduardo_: is that supported by icestorm yet?
<whitequark>
all-FOSS development tools are a priority
<eduardo_>
whitequark: yes.
<whitequark>
hrm
<whitequark>
39 I/Os
<whitequark>
that's just barely enough if I strip all possibility for extension (16-bit GPIF bus, 2 JTAG ports, 4 UART ports)
<whitequark>
(why so many? why the hell not, I want this to be the last JTAG adapter I build)
<whitequark>
eduardo_: any particular reason to go for ultraplus?
<azonenberg>
rqou: pic12f683
<azonenberg>
whitequark: it sounds like you're building a scaled down version of starshipraider
<whitequark>
azonenberg: quite possibly
<azonenberg>
starshipraider is going to use a 7a100t, using proprietary tools until the prjxray folks get more progress made
<azonenberg>
TCP offload in the FPGA, gig-e to the PC
<azonenberg>
it'll use my google protobuf FPGA library for the network protocol
<whitequark>
I aim for BOM ~ $25, full FOSS and parts I can get next door
<azonenberg>
yeah, starshipraider is going to be closer to $1K
<whitequark>
holy shit
<azonenberg>
but it will have 4 GB of RAM
<azonenberg>
a 7a100t
<azonenberg>
a 6-8 layer PCB
<azonenberg>
1G and 10G ethernet
<whitequark>
yeah no kill ilke overkill
<azonenberg>
well, its not just for jtag
<whitequark>
mine isnt just for jtag either
<azonenberg>
it'll have four 8-bit io expansion connectors
<azonenberg>
and be able to do LA, UART, i2c, jtag, etc on any of them
<azonenberg>
the default io card will be an 8-bit GPIO card with level-shifted output and comparator-thresholded input
<azonenberg>
Tolerant to +/- 12V if not more in fault conditions
* whitequark
. o O ( I can just configure the FPGA for passthrough and use fx2lafw lol)
<azonenberg>
Operating range from +1.2 to +5V logic levels
<azonenberg>
From DC to 500 Mbps
<whitequark>
"scaled down" doesnt fully quantify the difference between these
<azonenberg>
lol
<eduardo_>
whitequark: It has much more memory than all the rest (1 MBit on board, compared to 128k), it has 8 multipliers, the others have none. It is easy solderable as it is available in SG48 QFN, and its the FPGA I get the best price for.
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<azonenberg>
Do you know how hard it is to design a 1.2 to 5V variable voltage io cell with 500 Mbps data rates that doesn't die if you connect it to -12V DC? lol
<whitequark>
eduardo_: can't see why I'd need multipliers
<whitequark>
azonenberg: I can imagine
<azonenberg>
whitequark: my goal is to make the board indestructible while probing typical low voltage consumer electronics
<azonenberg>
i.e. as long as your wallwart supplies <= 12V and there's no boost converters on the board
<azonenberg>
you cannot destroy it even if you hook ground to the 12V rail and probe ground
<whitequark>
azonenberg: unless you have a relay on it :P
<azonenberg>
It won't function, the protection circuit will tristate the offending pin
<azonenberg>
But it wont die either
<whitequark>
without a flyback diode i guess
<eduardo_>
whitequark: BOM of 25 USD is easy .
<azonenberg>
yeah, but again thats kind of a special case
<whitequark>
eduardo_: $12 of that is CY7C68013A mind you
<azonenberg>
In the general case i want voltages found on typical embedded devices to be unable to hurt it
<whitequark>
HX8K is around $4
<whitequark>
the rest is probably PCB and connectors
<whitequark>
mind you I'm not making these in bulk...
<azonenberg>
whitequark: My current plan is to have a current limited DC path with clamp diodes and a series resistor
<whitequark>
though I might put it on tindie or whatever if I can get some sort of chinese board house to do PCBA
<azonenberg>
then an AC path capacitively coupled with a low capacitance ESD diode
<azonenberg>
Connect both paths at both ends
<azonenberg>
one path has low DC resistance but high parasitic capacitance (isolated by ferrites on either side to prevent loading down the AC path much) and tolerance to high DC voltages
<eduardo_>
whitequark: I can imagine you dont need the multipliers. but having on die memory of 1 MBit of Block memory is always good!
<azonenberg>
when shorted to a bad voltage the clamp diode shunts to ground, series resistor limits fault current, then a relay opens to open the circuit
<whitequark>
eduardo_: thats true, could use it as trace buffer or something
<azonenberg>
The other path cannot pass DC levels at all, but has ultra low parasitics and a protection diode to prevent AC transients from going through
<azonenberg>
when parallelled i should have pretty good performance from DC out to a few hundred MHz
<whitequark>
azonenberg: nice
<whitequark>
i'll put a zener on my board. maybe.
* whitequark
feels like she's building a plastic toy now
<eduardo_>
whitequark: ice40 Ultra is 6 USD in single piece.
<whitequark>
eduardo_: that's more than HX/LP
<whitequark>
not much more though
<whitequark>
I'll think about UP. I only have HX devboard though
<whitequark>
hm might also have LP devboard
<eduardo_>
whitrequark: we get about half of that price for volume.
<azonenberg>
whitequark: and the 4GB of DDR3 is intended to be used as trace/capture buffer
<azonenberg>
32 channel LA @ 500 Mbps gives me iirc about half a second of realtime capture
<azonenberg>
with no compression
<sorear>
i feel like "indestructible" and "cheap to replace" are properties that can be traded off against one another
<azonenberg>
sorear: Yes, this is inherently going to be expensive with the FPGA and RAM and such
<azonenberg>
So since it's not cheap to replace i'm going overkill on the io protection
<azonenberg>
i wanted a multi-voltage io cell anyway so i could work with anything from 1.2 to 5V logic
<azonenberg>
half the reason i'm building this is because i'm sick and tired of not having the right ftdi dongle in stock
<azonenberg>
this will just say "what voltage do you want" and give it to me
<azonenberg>
there will be a DAC driving a variable SMPS to produce any voltage i ask for in the range
<sorear>
mm
<azonenberg>
plus an ADC to monitor a provided reference voltage and track that
<eduardo_>
You always can do RLE of your traces with the FPGA to fit longer time in your trace memory
<azonenberg>
So i can either say "use this vccio" or "be 3.3V" etc
<azonenberg>
eduardo_: of course and my LA core does that already
<azonenberg>
so in practice i'd have >500ms of capture
<azonenberg>
But ddr3 is cheap enouhg if i'm gonna put ram on at all i might as well go 4GB
<azonenberg>
i can always not use it all :p
<azonenberg>
Oh, and this whole multi-voltage subsystem is going to be separate for each of the io cards
<eduardo_>
whitequark: most of it is getting the software (on the host side) working at full speed.
<azonenberg>
So you effectively get four io banks at different levels
<azonenberg>
In practice i expect i'd have a mix of io cards
<azonenberg>
so i could make one with can and rs485 transceivers
<whitequark>
eduardo_: pulseview is p good
<azonenberg>
i could make one with lvds
<azonenberg>
i could have one with analog io
<whitequark>
their analog view is sluggish but digital waveform viewer is very performant
<azonenberg>
etc
<azonenberg>
whitequark: Can it handle 10-50K WFM/s?
<azonenberg>
Or is there now hardware accel?
<azonenberg>
Because i am going to try ripping out my old waveform viewer and reimplementing the renderer in OpenGL when i build my oscilloscope
<azonenberg>
My plan is to have something capturing at 10 Gsps / 1 GHz bandwidth on four channels
<azonenberg>
Streaming over 10/40GbE to a PC
<azonenberg>
going into GPU memory
<azonenberg>
then do eye rendering, persistence, digital phosphor, etc in shaders
<azonenberg>
plus probably opencl-accelerated measurements of eye opening, BER, and so on
<eduardo_>
azonenberg: Will you build this before or after your tapeout of your FPGA? ;-)
<whitequark>
azonenberg: it has been using hardware accel for a very long time
<whitequark>
but it isn't a software-defined oscilloscope
<whitequark>
azonenberg: actually, scratch that
<whitequark>
it's not hardware-accelerated, it computes and uses mipmaps
<whitequark>
which explains why it can be slow on certain zoom levels...
<eduardo_>
whitequark: we contemplate to do a FX2 / FDTI or FX3 replacement tapeout with a Risc-V core as a proove of concept.
<whitequark>
eduardo_: cool!
* sorear
somewhat tangentially annoyed by the degree to which picorv32 and rocket dominate discourse
<azonenberg>
whitequark: exactly, i am basically trying to build a SDO :p
<azonenberg>
i want a combination of my PC with a nice GPU running this software, plus a 1U rackmount appliance with a front panel consisting of four SMA connectors and a SFP+
<azonenberg>
to be competitive with a decent lecroy or similar in terms of performance
<sorear>
although I'm actually not sure how big the gap is between minimally configured rocket and scr1/orca/pulpino/etc
<eduardo_>
Pulpino is not Yosys compatible
<pie_>
starshipraider sounds god tier
<eduardo_>
orca is VHDL
<pie_>
well demigod at least
<eduardo_>
orca is therefore not Yosys compatible.
<whitequark>
is there some VHDL-to-verilog translator?
<eduardo_>
whitequark: none which is working
<pie_>
release starshipraider and the 25$ one at the same time :P take the world by storm
<whitequark>
pie_: well I don't want to spend more than a week or two on this
<eduardo_>
VexRiscv and PicoRV32 are formally verified. As is Rocket. Pulpino tries to formaly verify their core too. Our goal is that all Risc-V cores are formally verified against "riscv-formal" from clifford wolf.
<eduardo_>
BOM of 25USD does not mean that it will be available at this price. its would mean more like 75-100 USD.
<whitequark>
eduardo_: I don't intend to profit from it
<whitequark>
so, however it costs me to hire a PCBA house, that much it will cost
<eduardo_>
whitequark: lets wait and see for what price you will offer your "??????" (name missing)
<whitequark>
sure
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<whitequark>
eduardo_: do ultraplus devices run at a frequency any higher?
<eduardo_>
whitequark: real designs run at 100MHz, not much of a difference between ice40 and ice40UltraPlus
<whitequark>
alright
<whitequark>
SPRAM is 70MHz
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<gruetzkopf>
soldered on or SO-DIMM?
<gruetzkopf>
argh, not fully scrolled
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<rqou>
azonenberg: does the pic12f683 need a high voltage programmer or is the pickit sufficient?
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<azonenberg_work>
the pickit is sufficient, i think it has a boost converter in it
<azonenberg_work>
pie_: starshipraider is intended to be a one stop shop for any and all <= 500 MHz embedded debug/development needs
<azonenberg_work>
as well as selected higher speed interfaces TBD
<azonenberg_work>
i'll probably put a GTP breakout header on it so you can do 1000base-X, SATA up to 3 or 6 Gbps, etc, maybe PCIe eventually
<rqou>
ah, so not like atmel with separate icsp and hv programmers
<pie_>
dumb question, how hard would it be to get it to do chip whisperer stuff :P
<gruetzkopf>
when this is released i need to have a 10G nic properly installed in my laptop