<azonenberg>
kc8apf: does that mean you have IOBs working?
<kc8apf>
no. It's similar to partial reconfiguration where Vivado is generating the harness but we've build the CLB config that goes inside the reconfigurable section
<azonenberg>
Ah, ok
<azonenberg>
So you blindly copied config bits from the IOBs
<azonenberg>
and then just patched in the clbs
<azonenberg>
So iob config remains unknown at this point?
<kc8apf>
well, I parse the top-level bitstream, compile symbolic names for all the CLB and routing bits inside our reconfig area, generate config frames, and then merge it all together into a bitstream that will program onto a board
<azonenberg>
ah ok
<kc8apf>
iob config is still unknown
<azonenberg>
so basically what i did for coolrunner macrocell bits when i only had the PLA figured out
<kc8apf>
primary milestone is having all the tools working well enough to write bitstreams that the devices will accept
<azonenberg>
ah ok, so this is first light for an x-ray bitstream actually touching hardware?
<kc8apf>
as more tiles are figured out, we can map them right into it
<kc8apf>
yup
<azonenberg>
:D
<azonenberg>
meanwhile, that github link i posted a few mins ago
<azonenberg>
was the first piece of RTL I wrote for fun in... this year? lol
<azonenberg>
i've been super busy with house stuff
<kc8apf>
now I'm going to go home and sleep. My fiance is rather upset with me for working so late figuring this out.
<azonenberg>
lol i'm home, my wife just rolled out of bed to say hi and ask if i emptied the dishwasher
<kc8apf>
heh
<azonenberg>
So yeah go sleep
* azonenberg
checks amazon to see if his threaded rods are coming soon
<azonenberg>
interesting
<azonenberg>
amazon says they're here
<azonenberg>
i saw a bunch of boxes, must have missed it?
<azonenberg>
WTF ups guy
<azonenberg>
puts 3 of 4 boxes at the front door and one at the side door
<azonenberg>
Welp, i think i have everything i need to hang my cable trays now
<rqou>
TIL H2SO4+KNO3->HNO3+KHSO4 is sloooooow
<rqou>
I'm so used to near-instant aqueous-phase reactions
<rqou>
azonenberg: i wouldn't be surprised if varint is easier to parse in hdl than in c
<azonenberg>
rqou: well my code is rather verbose, but it works and passes their test cases for unsigned
<azonenberg>
working on the signed coding now, should only be another minute or two
<azonenberg>
it's basically just moving the sign bit to the LSB
<azonenberg>
Parsing is fully combinatorial and happens as the input changes
<azonenberg>
You're of course free to register the output as you see fit, but i'm trying to avoid needing too deep a pipeline in the parser
<azonenberg>
So that i'll be able to work on streaming data with a clock equal to the data rate
<azonenberg>
Goal is to eventually put this parser in a TCP offload engine clocked off the RGMII RX clock
<azonenberg>
and handle gigabit protobuf data with only a couple of clocks of latency
<azonenberg>
On the TX side due to TCP checksums there will need to be one ethernet frame worth of buffering, which will add latency, but that shouldnt be a big deal
<azonenberg>
Basically when doing TX you'll tell the encoder what struct you want to emit
<azonenberg>
it'll ask you for each field
<azonenberg>
and you either say "skip it" for optional fields, or supply data
<azonenberg>
And it'll build the protobuf in real time as you go
<azonenberg>
For the time being, my parser will not support non-consecutive field ordering from concatenating two protobuf objects
<azonenberg>
i.e. it only supports protobufs that are the result of one object being serialized
<azonenberg>
But that's not a massive limitation
<azonenberg>
The plan is to compile the protobuf itself out to some kind of ROM image (not microcode per se, basically a machine readable description of what field is what type)
<azonenberg>
machine generate that as well as a bunch of named constants that name fields and enum values
<azonenberg>
and then have a single parser do all the work
<azonenberg>
Area wise the varint parser is 70 FFs, 191 LUT, 117 slice in 7 series
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<azonenberg>
sorear: yes
<azonenberg>
block or buffer depending on who you ask
<azonenberg>
but same thing
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<sorear>
This is probably a coming later item, but it'd be nice to have a reading list of Xilinx documents that define terms like "IOB" and "PIP" like the top-level IceStorm doc does
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<pie_>
jn, cool
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