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<rqou> azonenberg_work: the irc bot is still broken and i am sad :P
<azonenberg> Testing...
<azonenberg> It's claiming success on their end
<azonenberg> Huh
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<openfpga-github> openfpga/master ca4b624 Robert Ou: xc2par: Parse some more IO-related attributes...
<openfpga-github> openfpga/master 08a89df Robert Ou: xc2par: Fix misc. bugs...
<openfpga-github> [openfpga] rqou pushed 2 new commits to master: https://git.io/vNEg1
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<azonenberg> OK, now if i enable "message without join" let's see what happens
<rqou> that can't work because you have mode n enabled
<rqou> which presumably is because of the recent spamwaves
<azonenberg> Oh
<azonenberg> THAT is what broke it
<azonenberg> I didnt change that mode
<azonenberg> Do we want to leave the mode because spam?
<rqou> yeah
<azonenberg> and live with the join spam whenever somebody pushes?
<azonenberg> (i dont think there's a way to have the bot always remain joined)
<rqou> hmm, that's annoying
<azonenberg> I had -n set intentionally to allow external notices
<azonenberg> Which is how the bot worked
<azonenberg> i guess freenode changed that globally
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<openfpga-github> openfpga/master 5da8d65 Robert Ou: xc2par: Add a bunch of frontend reftests...
<openfpga-github> openfpga/master 2206398 Robert Ou: xc2par: Implement DATA_GATE attribute parsing...
<openfpga-github> [openfpga] rqou pushed 2 new commits to master: https://git.io/vNEwG
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<openfpga-github> openfpga/master da68859 Robert Ou: xc2par: Add some initial reftests for netlist.rs...
<openfpga-github> [openfpga] rqou pushed 1 new commit to master: https://git.io/vNEr0
<rqou> wow i updated vlc and now all of its fonts look like complete shit
<rqou> azonenberg: do you happen to know if a slg46620v is faster or slower than an oldschool pal/gal?
<azonenberg> rqou: no experience with the oldschool ones
<azonenberg> so cant say
<azonenberg> A coolrunner is certainly massively faster
<rqou> from what i can see gp4 is slow as shit
<azonenberg> it is
<rqou> a coolrunner is slower than some oldschool pal/gals :P
<azonenberg> The advantage is the mixed signal and low power plus ultra-tiny package size
<azonenberg> And, more importantly
<azonenberg> wide supply range
<azonenberg> Single supply 1.8 to 5.5V is something most other PLDs cant do
<azonenberg> it has MCU-level Vdd flexibility
<rqou> but it's imho barely even usable at 1.8v because it's so slow
<rqou> e.g. 20ns for a lut4?!
<azonenberg> Yeah its meant for glue logic at that speed
<azonenberg> its not super fas
<azonenberg> fast*
<azonenberg> i havent looked at timing but the new greenpak stuff is out btw
<rqou> but oldschool plds were also meant for glue logic :P
<azonenberg> first dialogsemi release
<azonenberg> Has full bitstream docs
<azonenberg> and i2c in-system programmable :D
<rqou> hey, i just thought of a troll feature request for yosys: read_abel :P
<rqou> at least it would be easier than read_vhdl :P
<sorear> what's typical for a lut4 these days?
<rqou> idk actually, ~5ns??
<azonenberg> sorear: On what technology node? :p
<azonenberg> Some random values for LUT delay...
<azonenberg> GreenPAK LUT4, 1.8V - 16-19 ns (falling/rising)
<azonenberg> GreenPAK LUT4, 3.3V - 6.6 - 7.4 ns
<azonenberg> GreenPAK LUT4, 5V - 4.6 - 4.9 ns
<rqou> s6?
<rqou> a7?
<sorear> azonenberg: the more numbers the better
* azonenberg continues skimming datasheets
<azonenberg> (those numbers include routing delay, btw - not just the lut)
<azonenberg> ice40 LP: 2.6 ns including routing delay (extrapolated from published number for 16:1 mux which is two levels of logic)
<azonenberg> Spartan-3A, -4 speed: 0.71 ns (LUT only, no routing delay)
<rqou> O_o that fast?
<azonenberg> Spartan-6, -2 speed: 0.26 ns
<rqou> the routing probably dominates in this case
<azonenberg> Yes, in my experience routing is typically ~2x logic in a typical xilinx design and sometimes more
<azonenberg> Anyway, continuing
<sorear> I think the numbers in https://github.com/cliffordwolf/icestorm/blob/master/icefuzz/timings_lp8k.txt are in picoseconds although there's a lot of interplay between code and data I haven't understood
<azonenberg> Artix-7, -2 speed: 0.11 ns
<azonenberg> Kintex-7, -2 speed: 0.05 ns (datasheet is really losing precision here, thats only 1 significant figure)
<rqou> v7u+? :P
<azonenberg> rqou: let me check
<azonenberg> either U or U+ they stopped publishing full CLB timing
<rqou> lolol
<azonenberg> i forget which
<azonenberg> yeah starting ultrascale they dont publish full timing data
<azonenberg> the only supported timing analysis is to run their software
<rqou> how far we've come from doing timing analysis with fingers :P
<azonenberg> lol
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<rqou> hey azonenberg_work, i forgot if i asked this already, but do you think an ice40 hx8k is large enough to fit ethernet+udp?
<azonenberg_work> rqou: Dont know
<azonenberg_work> but, probably
<azonenberg_work> Not sure how much else
<azonenberg_work> ipv4? v6? dhcp? hard coded ip? slaac?
<rqou> meh, don't care about those
<azonenberg_work> If you want to spit out hard coded packets with a fixed source/dest IP and port number
<azonenberg_work> no udp checksum
<azonenberg_work> and just rely on the ethernet crc32
<azonenberg_work> you could probably fit it in something a lot smaller than the 8k
<rqou> i want to receive too
<azonenberg_work> Still easy enough
<sorear> 10Mbit?
<azonenberg_work> rely on the switch to always send things to your mac (or do a quick 48-bit comparison against your hard coded mac, thats... 16 luts)
<azonenberg_work> ignore the ip address
<azonenberg_work> You'll have to implement ARP as a minimum, though, to receive
<azonenberg_work> Still not a big deal
<rqou> hrm
<azonenberg_work> You can do it i think
<azonenberg_work> But implement it in sim and test
<azonenberg_work> See how big it is
<rqou> i wonder how cheaply i can get a three-port switch :P
<rqou> use a microcontroller to do all the management stuff and the fpga to actually move the data
<rqou> overengineered?
<rqou> azonenberg_work: how would you personally feel about designing a board built around https://www.aliexpress.com/store/product/Free-shipping-QCA8334-AL3C-QCA8334-AL3C-100-new-original-QFN88-5pcs/2289093_32702376514.html
<rqou> (yes, including this specific method of obtaining chips :P )
<rqou> hmm this particular chip is actually not optimal
<rqou> it only has one rgmii port
<rqou> azonenberg_work: do you have a preferred switch chip that doesn't require finding a leaked datasheet?
<azonenberg_work> No
<azonenberg_work> in fact, the lack of such parts is what prompted me to start working on buliding an FPGA switch IP
<azonenberg_work> forget the switch asic, have the fpga hook up to a couple of phys
<azonenberg_work> Or skip the phy if you just want mii to the MCU or something
<rqou> i wanted the fpga and mcu to both use mii to a switch :P
<rqou> disable mac learning and make it look like one device
<rqou> apparently these parts do exist, but they're all weird
<rqou> because i'm not falling into the normal use cases
<azonenberg_work> lol
<rqou> ah, there's the KSZ9897
<rqou> nobody has the configuration that i want, which is 2x RGMII/RMII/MII, 1x 10/100/1000-baseT, 1x SGMII/baseX
<azonenberg_work> That sounds like an artix7 plus a ksz9031
<azonenberg_work> :p
<azonenberg_work> Tell you what, if you seriously plan to do this i'll try to finish my switch core
<azonenberg_work> i have a RGMII MAC and a 1000baseX MAC already
<azonenberg_work> and a mac table supporting vlans and learning
<rqou> i mean, if i didn't mind an even higher bom cost, i would just use an extra phy and then use the KSZ9897**S**
<azonenberg_work> all i'd have to do is the forwarding
<rqou> i don't want a DIY switch
<rqou> the switch is literally being used as a giant hack to "fuse" two ethernet connections into one
<rqou> to offload work from the shitty fpgas i plan to use
<azonenberg_work> lol
<azonenberg_work> meanwhile my plan was to replace my old ciscos
<azonenberg_work> with a custom 1U monster :p
<rqou> alternately i can use the ti micros with onboard ethernet phys
<rqou> although i heard they suck
<azonenberg_work> Do you actually need gigabit?
<azonenberg_work> or is 10/100 OK
<rqou> 10/100 might be ok
<azonenberg_work> TRAGICLASER
<azonenberg_work> :D
<rqou> goddammit no
<rqou> also, the target is an ice40
<rqou> hey the KSZ9897R seems to be pretty decent
<rqou> at least it doesn't have a bajillion straps :P
<azonenberg_work> lol
<mithro> azonenberg_work: Ha -> https://github.com/azonenberg/protohdl
<rqou> wtf
<rqou> why azonenberg_work
<azonenberg_work> Because there is currently no good way to send data from a PC to an FPGA/ASIC in a structrured form without writing two separate implementations of the protocol
<azonenberg_work> protobufs solve this problem for e.g. C to java
<azonenberg_work> one of the reasons libjtaghal's socket protocol currently doesn't use protobufs is that i wanted it to be FPGA-parseable
<azonenberg_work> so STARSHIPRAIDER could implement it
<azonenberg_work> and i didnt want to write a custom protobuf parser on one side and then use a .proto on the other
<azonenberg_work> so i want to write the FPGA parser generator once and be done with it
<rqou> why not bson or some other binary-json format?
<rqou> also, a while back a friend and i designed a custom DSL for essentially this purpose
<azonenberg_work> It'll take in 8 bits at an arbitrary clock rate, at 250 MHz that's 2 Gbps and most 7-series etc parts can go even faster
<rqou> but it _sucked_ to use because we used yaml and it was way too verbose
<azonenberg_work> So it wont be able to max 10G but it'll be able to saturate gig or run several fat flows over a 10G pipe
<rqou> we didn't have fpga support of course
<azonenberg_work> And for my 10G applications i mostly expect a low bandwidth control channel on one socket using protobufs
<azonenberg_work> and then a high bandwidth data channel that's just (say) raw I/Q
<azonenberg_work> no parsing needed
<azonenberg_work> this is explicitly intended for PC-to-FPGA comms over a LAN
<azonenberg_work> but it could work over pcie etc too
<rqou> IIRC i looked at protobufs and didn't like using it
<azonenberg_work> I have a good idea for how the parser will be structured
<azonenberg_work> i just have to implement
<azonenberg_work> Wanted to get the repo up so i could make some wiki notes and design stuff then implement later
<azonenberg_work> My eventual plan is for all of starshipraider's virtual instruments to provide a .proto
<rqou> yeah, varints are a pain to decode, that was a big reason i didn't go with protobufs
<azonenberg_work> so you can talk to them over a lan from an arbitrary language
<rqou> my friend and i basically wanted "take c struct declarations (without the need for forward declarations) and generate parsers in scripting languages"
<rqou> but we didn't want to write a c parser and used yaml instead, big mistake
<azonenberg_work> lol
<azonenberg_work> I'm actually hoping i can split this up so i have a parser generator, a .proto wire format parser, and a .proto text file parser
<azonenberg_work> So i can reuse the backend to create a parser for, say, TCP
<azonenberg_work> or IP
<rqou> oh yeah, another reason i disliked proto was that its wire types aren't great
<rqou> i basically never want varint, and i wanted a lot of u8/u16
<rqou> azonenberg_work: what's mii "MAC mode" vs "PHY mode?"
<rqou> oh nvm, that's some quirk specific to _MII_, not RMII/RGMII
<azonenberg_work> Unlike GMII, MII uses one clock for both buses
<azonenberg_work> So it probably specifies who drives it
<azonenberg_work> GMII is source synchronous and the only real difference is who drives the MDIO bus (if it's even used)
<rqou> if i use rgmii between an fpga and a switch, can i force it to "always gigabit?"
<rqou> now i get "tri-speed support" for "free" :P
<azonenberg_work> Yes you can autonegotiate to gig
<azonenberg_work> and say you dont support 10/100
<azonenberg_work> a sane switch should do that just fine
<rqou> apparently this switch can't negotiate on the rgmii port
<rqou> the rgmii port is set by a strap
<azonenberg_work> Lol
<azonenberg_work> That works too then
<rqou> of course, the baseT ports do
<azonenberg_work> Force to gig and call it good
<azonenberg_work> I guess that makes sense actually
<rqou> and the switch will buffer packets for me
<rqou> i think?
<sorear> do the common binary-JSON formats guarantee field sorting? I notice that protobuf doesn't
<rqou> can't you just apply the jwt field sorting while encoding if you want that?
<rqou> hrm, i swear jws/jwt/jose defined a way to sort fields in an object, but apparently not??
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<rqou> azonenberg: lolol crash an iot/embedded piece of crap in seconds by just sending it random dns replies: https://github.com/sgayou/medfusion-4000-research/blob/master/doc/README.md
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<jn> rqou: 90s style
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<mIKEjONES> digshadow: yo
<digshadow> mIKEjONES: replied PM
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