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<gruetzkopf> usa wiring is weird
<gruetzkopf> here we use NYM-J marked cable (double-insulated, solid conductors) for basically everything fixed-install
<gruetzkopf> the other type still seeing some use is NYIF-J which is mostly the same setup, but with wires side-by-side for installation in plaster
<gruetzkopf> and rarely single conductors in plastic conduit
<gruetzkopf> (our earth wire is almost alway insulated as well)
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<pie_> something something dude wrote a crack for altera (not sure if hardware or software...) https://www.youtube.com/watch?v=C8txvmXUIJQ
<pie_> bakc in the day
* pie_ preoccupied
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<rqou> just for reference
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<rqou> O_o according to another 34c3 talk, there's a north korean tablet computer in the stanford library
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<ZipCPU> rqou: Did you see the comment on reddit.com/r/yosys about adapting yosys for (another) CPLD?
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<ZipCPU> Having gone through the process of implementing a CPLD techmap and integrating it into yosys, I thought you might have some of the best background to answer his question.
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<rqou> ZipCPU: ah, asking for a 22V10?
<ZipCPU> Yeah, that was the question.
<rqou> i wouldn't bother, 22V10s probably have even more weird restrictions than modern cplds
<ZipCPU> So ... I'm not the one asking.
<ZipCPU> I just want to see if I can find someone to answer the query.
<ZipCPU> ('Cause ... I don't know the answer ... ;D)
<rqou> eh, i don't use Reddit
<rqou> ooh wait
<rqou> yes, this is actually easy
<rqou> 22V10s have so few features that this will work
<rqou> the problem is that afaik the programming algorithms are proprietary
<ZipCPU> Maybe he knows something?
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<awygle> So I broke my foot.
<rqou> alright, fine i'll reply on reddit
<rqou> awygle: :(
<awygle> rqou: quite
<ZipCPU> Thanks, rqou!
<ZipCPU> awygle: :(
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<rqou> it's pretty hilarious that mapping to a 22v10 seems easier than mapping to a modern cpld
<rqou> the key reason being that on a 22v10 it either fits or you're screwed
<rqou> whereas on a modern cpld there's quite a bit of "maybe you can twiddle this thing?"
<rqou> wait wait wait
<rqou> the person asking for 22V10 support
<rqou> is that Robert Baruch?
<qu1j0t3> his ac is @babbageboole
<qu1j0t3> on twitter anyhow
<rqou> yeah, since i know him irl i'm more interested in his feature request
<rqou> also i just accidentally found a bug in abc
<rqou> "cover" with only 1 input infinite-loops abc
<rqou> oh wow PAL/GAL software really is garbage
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<rqou> azonenberg_work: what do you think about a distraction to add 22v10 support to yosys?
<azonenberg_work> rqou: i have negative free time right now
<azonenberg_work> but if you want to work on it, i wouldnt complain
<rqou> apparently robert baruch wants it?
<azonenberg_work> Like i said, i have no time but i wont complain if somebody else works on it
<rqou> azonenberg_work: how do you feel about me pulling my jed library into a separate module?
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<azonenberg_work> probably makes sense to be more modular than less
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<azonenberg_work> esp if we want to add xpla3 or xc9500* eventually
<rqou> azonenberg_work: apparently xilinx jed files break the rules and are technically invalid
<rqou> they don't have a design header field
<azonenberg_work> Surprise surprise
<azonenberg_work> They break the rules in lots of ways
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<rqou> I'm probably going to have to end up defining a "Xilinx" mode and a "standard" mode
<rqou> although i think I can _write_ a file that's legal in both
<rqou> reading is fun though since I sniff for a hot comment with the device name
<rqou> azonenberg_work: hey, how divergent is our yosys right now?
<azonenberg_work> Dont know, i can check when i get home
<azonenberg_work> just pushed a merge to latest so we have all of upstream in our fork
<azonenberg_work> plus whatever unmerged stuff we've been working on
<rqou> which is currently a giant mess
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<azonenberg_work> Indeed
<azonenberg_work> Buut until this constructino is done i doubt i will have time to do anything about it :p
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<rqou> i'm trying to fix it right now
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