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<rqou> scada is hilarious
<rqou> worse than internet of shit sometimes
<gruetzkopf> oh yeah i hope i didn't make too big of a mess of that
<rqou> i messaged you pointing out that all of the videos have the intro way too loud vs the rest of the audio
<gruetzkopf> yeah, the videos themselves are fairly quiet this year
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<azonenberg> Have you tested it?
<rqou> no
<azonenberg> Also that's a pic12f683 right?
<azonenberg> i'd recognize that die anywhere :p
<rqou> yeah how can you tell? :P
<azonenberg> rough size, dip8 package, coloration matches
<rqou> lol
<azonenberg> size and relative positions of flash, eeprom, and ADC blocks (all visible at this magnification, you cant actualyl tell what they are but i've seen the chip up close so i know)
<rqou> btw dips are actually more difficult than qfps
<azonenberg> Yes they are
<azonenberg> I normally pre-drill the top with an endmill
<azonenberg> to get down to maybe 200um above the bond wires
<azonenberg> then finish with acid
<azonenberg> With a large QFP you can skip that and just etch all the way through
<rqou> yeah
<azonenberg> If i'm trying to recover a bare die, if at all possible, I'll use a QFN or WLCSP or something like that
<azonenberg> while if i want it live, i'll use the largest package i reasonably can
<rqou> also, i never realized just how space-constrained a standard dip is
<azonenberg> just wait till you decap a large QFP
<azonenberg> giant leadframe coming down to super tiny points near the die for wirebonding
<azonenberg> try doing a tqfp144 with a small die :p
<rqou> i did that before
<rqou> that's how i ended up with an "unintended uncontrolled reaction"
<azonenberg> Lol
<azonenberg> what did you do, use piranha?
<rqou> whole chip in hot sulfuric acid
<rqou> that was the xc95288xl
<awygle> Gonna guess piranha is a brand name or nickname or something, but I'll treasure that mental image
<rqou> awygle: sulfuric acid+hydrogen peroxide
<rqou> very strong oxidizer
<rqou> your surface will definitely not have organic contaminants afterwards :P
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<pie__> * whitequark
<pie__> its pretty late in the US right now xD
<gruetzkopf> rqou: once you get better i have a fem motorola 68360 for you
<gruetzkopf> *few
* pie__ ponders
<pie__> i need to start making some friends at the chem department :D
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<Dolu> Some update about VexRiscv performance (Look at "There is a summary of the configuration") https://github.com/SpinalHDL/VexRiscv/blob/master/README.md
<whitequark> pie__: seems overetched
<Dolu> Also it look like the SiFive prepacked GCC version has some issues with the RV32 performances
<Dolu> Maybe the precompiled libraries weren't compiled in -O2
<rqou> hrm, none of my live-decapped DIPs have intact bond wires
<rqou> but all of the QFPs do
<rqou> unfortunately they're also all dirty
<pie__> s/ie/die/
<pie__> rqou, dumb idea, could you electroplate the wires before ultrasonic cleaning to strengthen them?
<pie__> whitequark, huh.
<rqou> these haven't been ultrasonically cleaned
<pie__> yeah i know just wondering
<pie__> actuallyi gues that really doesnt make any sense because you need an anode and a cathode
* pie__ goes back to doing whatever
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<azonenberg> rqou: oh wait
<azonenberg> the pic12f683
<azonenberg> how did you decap it? what acid(s)
<azonenberg> And what date code are they?
<sorear> Dolu: i'd be curious to know what kind of issues
<azonenberg> i derped and forgot to tell you when you were picking that chip *facepalm*
<azonenberg> As of mid 2017 date codes, if not earlier (i forget when the chance notice went out)
<azonenberg> MCHP is using copper bond wires and not gold
<azonenberg> for the 683
<azonenberg> They're a lot more fragile
<pie_> pwnd :P
<pie_> wait, who gives notices about stuff like this?
<pie_> or is this a work thing
<azonenberg> pie_: most chip vendors give change notices about very small things
<azonenberg> you just have to know where to look for them if you're not a volume customer who gets the email
<azonenberg> they post the changes on the website etc
<azonenberg> they'll talk about moving a chip from one fab to another
<azonenberg> Or changing the wafer size
<pie_> oh. huh.
<azonenberg> Or qualifying a new package vendor
<azonenberg> etc
<azonenberg> And changing bond wire material is one of those things
<azonenberg> they're a source of a lot of useful RE info
<azonenberg> like, when they qualify a new fab
<pie_> does anyone aggregate these sources somewhere?
<azonenberg> they'll usually mention who the existing fab was
<pie_> yeah that does sound very useful
<azonenberg> Not that i know of, i scrpae things manually as needed
<azonenberg> when looking at a particular chip
<azonenberg> oh it was 2014
<azonenberg> lol
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<pie__> i wonder if you can wireshark the pci bus
<pie__> shows how much i know about hardware...
<pie__> id guess you cant beccause its probably 1) point to point 2) too fast 3) it would basically result in a feedback loop
<jn> pie__: pci or pcie?
<pie__> i dunno
<pie__> both i guess
<pie__> well 2 doesnt actually matter if you were trying to capture from "inside" the system
<pie__> its more about whether relative speed would work
<whitequark> pie__: you could run your thing in a vm
<whitequark> and instrument that
<Dolu> sorear: I haven't checked more, but the delta is big, 30% less performance in the dhrystone benchmark
<sorear> Dolu: delta between what and what?
<pie__> whitequark, oh huh true
<Dolu> Another funny thing is that with https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-20171231-x86_64-linux-centos6.tar.gz i got system call in my compiled dhrystone binaries instead of barmetal stuff XD
<pie__> (i guesssss)
<sorear> Dolu: which is the fast one and which is the slow one?
<Dolu> the fastest one is the compiled from sources riscv-gnu-toolchain
<Dolu> by 30%
<sorear> straw poll: of the people here who are into riscv stuff and aren't in #riscv, is it by choice or because we suck at advertising?
<cr1901_modern> sorear: ETOOMANYCHANNELS
<Dolu> advertising for me ^^
<cr1901_modern> But seeing as I'd like to ask the boom_cpu creator some q's, I prob should at least idle/add it to my list
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<awygle> whitequark: is instrumenting pcie using a vm a "standard" thing or would it involve e.g. qemu hacking?
<sorear> so I'm hazy on the precise dates but dhrystone makes exceptionally heavy use of global variable access and 30% is about right for the difference between PC-relative and GP-relative accesses
<whitequark> awygle: no idea
<whitequark> it's just obviously possible
<awygle> sure, it's a good solution
<sorear> [more cynically I might describe the global pointer stuff as an almost dhrystone-specific optimization]
<Dolu> sorear : XD
<Dolu> Sadness that the dhrystone benchmark is is only about 300 instruction per loop too
<Dolu> I will check tomorrow the GP/PC relative stuff
<cr1901_modern> What level of pcie would a VM emulate? TLP? Link-Layer?
<whitequark> none of it
<whitequark> you just intercept memory accesses
<whitequark> come to think of it this doesn't handle DMA by the device
<cr1901_modern> I wouldn't be surprised if there's a opt-in way to do that in Linux (like UIO), but I know nothing about it
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<whitequark> what?
<whitequark> that makes no sense
<pie__> yeah thats why the lot of s on the guessss :P
<gruetzkopf> what do you want to do?
<cyrozap> pie__: It's fairly straightforward to sniff PCIe, it just depends at what level you want to stiff at. If you want to see the TLP layer, you'll need some hardware, but it doesn't need to be particularyly fast--even RS232 speeds will work: https://media.ccc.de/v/33c3-7946-console_hacking_2016#t=465
<cyrozap> pie__: To build on what whitequark was saying, if you just want enough information to, for example, write a driver, you can run the program in a VM and do PCIe passthrough, then log all the accesses from the VM.
<gruetzkopf> if you need to look at a linux driver you don't have source for, mmiotrace is your friend
<cyrozap> pie__: It is a _little_ tricky, since by default qemu will just let the VM mmap the PCIe device's address space, so you have to configure it to not do that.
<sorear> yeah this whole thing depends on what you're actually trying to do
<awygle> what if i wanted to develop pcie hardware that was drop-in compatible with an existing linux driver?
<cyrozap> awygle: Then just read the driver sources and base your work on that :P
<awygle> cyrozap: well yes :P but since you have to deal with TLPs in the hardware/HDL, it'd be nice (but not necessary) to be able to look at them
<awygle> for debugging etc
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<cyrozap> awygle: But the kernel doesn't care about TLP layer stuff, it's just memory reads and writes. I mean, yes, the lower layers of the stack care about that, but that's like saying you need to care about Ethernet frames when writing a userspace TCP/IP application--if you need to debug the lower layer protocols, that's done independently from the upper layer protocols.
<awygle> cyrozap: sure but from wireshark you can get Ethernet, IP, TCP, or HTTP depending on what you need. it's true that you probably can't get TLPs from Linux or even qemu because of how pcie is, but it would be cool if you could.
<cyrozap> awygle: Oh, yeah, it totally would. I use Wireshark for USB stuff all the time and it's fantastic. Doesn't help you with the USB PHY protocols, though--you still need a scope/LA/low-level protocol analyzer for that.
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