<sorear>
as long as it doesn't have .DS_Store files I'm happy
<q3k>
you can lint out .DS_Store files
<q3k>
you can't fix an engineering culture mistake like this
<Bike>
are there three distinct versioning systems here
<q3k>
s,mistake,problem,
azonenberg_work has joined ##openfpga
azonenberg_work has quit [Ping timeout: 260 seconds]
pie_ has joined ##openfpga
m_t has quit [Quit: Leaving]
<awygle>
the build system at $DAYJOB is so bad i barely notice such things anymore
<awygle>
(they know that, to be fair, and are working on fixing it)
<q3k>
i get paid to fix shit like this so I notice immediately :P
azonenberg_work has joined ##openfpga
ZipCPU|Laptop has quit [Ping timeout: 276 seconds]
eightdot has quit [Ping timeout: 268 seconds]
eightdot has joined ##openfpga
mumptai_ has joined ##openfpga
mumptai has quit [Ping timeout: 256 seconds]
rohitksingh_work has joined ##openfpga
unixb0y_ has joined ##openfpga
<unixb0y_>
I setup a BNC 😊
futarisIRCcloud has quit [Quit: Connection closed for inactivity]
ZipCPU|Laptop has joined ##openfpga
Bike has quit [Quit: Lost terminal]
kem_ has quit [Quit: Connection closed for inactivity]
azonenberg_work has quit [Ping timeout: 248 seconds]
futarisIRCcloud has joined ##openfpga
azonenberg_work has joined ##openfpga
pie_ has quit [Ping timeout: 240 seconds]
pie_ has joined ##openfpga
pie_ has quit [Ping timeout: 248 seconds]
thallia has quit [Ping timeout: 240 seconds]
thallia has joined ##openfpga
<eduardo__>
q3k: opnmessd was probably a funded reserach project of the south korean university. They had the requirement written in the funding to publish everything on github, but did stiock with theior old development practise.
<eduardo__>
q3k: they had no intention to build a community, but only to get funding for their team.
<eduardo__>
q3k: it is a project in itself to build a sustainable community arround a sw project. for which you usually dont get funding ( do you listen f****** Darpa?)
<eduardo__>
q3k: reserach funding is time limited, so after funding terminates, the project falls appart.
<eduardo__>
q3k: you can only hope that enough was left after the project that someone can pick up the parts (which sometimes is possible if the original project people wanted tp leave something which can ba taken up by someone else)
<rqou>
oh wtf, jupyter managed to f*ck up my previous problem set pdf
<eduardo__>
q3k: if ther original people didnt care about the people who will come after them, then it is usually just garbage which they left behind.
<rqou>
converting it again yields different (correct) results
<rqou>
why is is so friggin hard to just format some pretty equations?!
<eduardo>
q3k: So the question is if there is any code which is useful and worth the be salvaged from that project and put into a proper git repository. It might be that the design is very HW specific.
<eduardo>
q3k: where you are currently located? (thats relevant for invoicing)
rohitksingh_work has quit [Read error: Connection reset by peer]
unixb0y has quit [Quit: ZNC 1.6.5+deb1 - http://znc.in]
unixb0y has joined ##openfpga
unixb0y has quit [Client Quit]
unixb0y has joined ##openfpga
rk[ghost] has quit [Ping timeout: 256 seconds]
rk[ghost] has joined ##openfpga
rohitksingh has joined ##openfpga
unixb0y has quit [Quit: ZNC 1.6.5+deb1 - http://znc.in]
pie_ has quit [Ping timeout: 248 seconds]
ondrej2 has quit [Read error: Connection reset by peer]
ondrej2 has joined ##openfpga
rohitksingh has quit [Quit: Leaving.]
pie_ has joined ##openfpga
cr1901_modern has quit [Read error: Connection reset by peer]
cr1901_modern has joined ##openfpga
kem_ has joined ##openfpga
unixb0y has joined ##openfpga
m_t has quit [Quit: Leaving]
azonenberg_work has quit [Ping timeout: 260 seconds]
<awygle>
rqou: data io is actually a great place to work. the work isn't terribly inspiring but my bosses have been nothing but great so far
<awygle>
I just like to whine :-P
m_w has joined ##openfpga
azonenberg_work has joined ##openfpga
<unixb0y>
Hey guys what’s the best way to get data out of the FPGA (debugging)?
<cr1901_modern>
awygle: I was given an old Data I/O EPROM programmer. I scrapped it for parts when I couldn't get it to work. The 41256 DRAM lives on in my PC AT. The LCD and keypad I use for parts. The 8088-5 is a spare.
<cr1901_modern>
Probably not my proudest moment collecting vintage crap, but it is what it is :/
<unixb0y>
Thanks, I'll have a look at that. @ZipCPU
<rqou>
years ago my father's employer had an already-ancient-back-then parallel port data io programmer
<rqou>
the programmer worked just fine, but they had lost the software install media and nobody wanted to deal with that
<rqou>
so there was an ancient computer connected to the programmer that could only have data exchanged using floppy disks
<rqou>
at some point someone got the machine infected with a nasty virus
<rqou>
nobody could get it removed, so eventually somebody figured out how to "neuter" some floppy disks so that it would not infect new machines
<rqou>
but the virus though it was infected and wouldn't reinfect it
<ZipCPU>
unixb0y: That was sort of the purpose. There are actually *many* posts on the topic at zipcpu.com, perhaps not as well organized as I might like.
<unixb0y>
ZipCPU: Okay :D I must say your website is pretty neat, esp. "Avoiding FPGA hell" ;)
<ZipCPU>
Been there too, huh?
<unixb0y>
Sure ;)
<unixb0y>
I currently need a way to check if my module does the right things as my VGA module isn't done yet...
<rqou>
so the de-facto procedure to program something was "get a special red floppy, disable the normal endpoint AV, copy a hex file onto it, and transfer to the programmer machine"
<unixb0y>
My project is kind of educational-oriented so I want to eventually have a nice graphical output. But for now, console output of the algorithm itself would be awesome
<rqou>
I'm sure there won't be any compliance issues with this solution at all :P
<ZipCPU>
The other cool thing about the debugging bus, is that you can place wbscope's on it and get a debugging trace out from anywhere within your design.
<ZipCPU>
There's an example of that in the demo project that I pointed you at earlier.
<unixb0y>
Very nice!
<unixb0y>
Unfortunately, I just lost a part of my IRC history *facepalm*
<ZipCPU>
I should mention, I've also connected graphics to that C++ based interface. It's just necessarily fast.
<rqou>
azonenberg: idk if you missed me asking earlier, but do you know much about the state of the art in automated deobfuscation and/or better obfuscation?
mumptai has joined ##openfpga
user10032 has joined ##openfpga
rk[ghost] has quit [Ping timeout: 268 seconds]
rk[ghost] has joined ##openfpga
X-Scale has quit [Read error: Connection reset by peer]
X-Scale has joined ##openfpga
reportingsjr has quit [Quit: WeeChat 1.4]
m_t has joined ##openfpga
<awygle>
cr1901_modern: apparently those old DRAM modules are worth a fortune, and old customers always complain that we won't sell them for a song anymore
<awygle>
(or so i've eavesdropped from coworkers)
m_w has quit [Quit: leaving]
m_w has joined ##openfpga
strfry has quit [Quit: WeeChat 1.9]
<cr1901_modern>
Uhhh... you can get a pack of 9 for fairly cheap on Ebay.
<rqou>
i guess it depends on what type exactly?
<rqou>
maybe pre-FPM dram is really expensive?
genii has joined ##openfpga
<rqou>
legacy hardware is legacy
<rqou>
i remember reading a report from ~2012 complaining yet again about counterfeit parts in us military supply chains and they actually mentioned some specific part numbers
<rqou>
USG was trying to buy an XC3000-series
<rqou>
aka "what did you think would happen?"
<awygle>
maybe that's not the particular part, I'm pretty sure we don't even support EPROM programmers for $HILARIOUS_SUM
<awygle>
Or maybe we charge to upcheck them for production *shrug*
<rqou>
so if someone asked data io "i lost my install floppy from the late 1980s" would they help?
<awygle>
Depends on the product I expect. Worth asking.
<rqou>
lol my father doesn't actually have that ancient programmer anymore so it's moot
<azonenberg_work>
rqou: i do not
<rqou>
awygle: just to make you sad, I've obtained a TL866 programmer instead
<azonenberg_work>
rqou: if they needed xc4000 series i'd say go to RPI and buy up the stuff the "advanced computer hardware design" class uses
<azonenberg_work>
then they'll have to upgrade :D
<rqou>
lolol
<rqou>
not even an old virtex-2?
<rqou>
i thought that was the classic university lab device
<awygle>
Random Fpga thought - if you synthesized a module, P&R'd it, parsed the bitstream output, and then annotated the synthesized net list with RLOC constraints according to the placement, could you fake relocatable prerouted subcircuits