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<awygle> this is simultaneously really interesting and deeply weird
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<azonenberg> digshadow, mithro, kc8apf__: Have any of you looked at the config process for SLR-based devices?
<azonenberg> it doesn't appear to be documented anywhere
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<mithro> azonenberg: SLR?
<sorear> super logic regions?
<azonenberg> Yes
<azonenberg> They have a 6*N bit JTAG IR for N SLRs
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<azonenberg> there's a "nop" instruction you can load into a SLR to execute a command only there, or you can broadcast it to the whole chip
<azonenberg> When configuring, they have a separate CFG_IN for each SLR in a strange order i dont fully understand
<azonenberg> in particular the usual sync word isnt where i expect it
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<azonenberg> Continuing to tinker with SLR-based FPGA JTAG config
<azonenberg> this is...interesting to say the least
<azonenberg> i guess the SLR dies must have some kind of strap pin to specify what address range they have
<azonenberg> I expected one of two things
<azonenberg> 1) you split the bitstream up by frame address and write frames to the SLR they live in
<azonenberg> 2) you send the whole bitstream to the master SLR and it pushes it out from there
<azonenberg> Turns out, both are wrong
<azonenberg> what you ACTUALLY do is, send the entire bitstream to one SLR at a time
<azonenberg> it acts on the config state machine for initial setup, then ignores everything written to FDRI that isn't for that die
<azonenberg> Then processes the CRC etc just like a monolithic die
<azonenberg> Then at the end, you send START; DESYNC to two of the SLRs (interestingly enough only the left and middle get this, not the right) individually
<azonenberg> then push what i think is a bunch of dummy frames but i havent parsed the stuff after the desync to confirm
<azonenberg> then send a bunch of dummy clocks, JSTART, and you're good to go
<azonenberg> i have yet to code this up myself and test it on real hardware but i think i understand how it works (mostly)
<azonenberg> I cant guarantee everything i've figured out generalizes to other devices yet, so far i'm only looking at the XCVU9P
<azonenberg> i don't have licenses for any other non-monolithic parts
<sorear> so configuring a 3-SLR part takes 9 times as long as configuring a 1-SLR part?
<azonenberg> Over JTAG, i think so
<azonenberg> This seems stupidly inefficient but i'm parsing the SVF
<azonenberg> the key bit is the type-2 write transactoins
<sorear> (SLRs per XCVU9P?)
<azonenberg> lookign at the .bit file itself, the same sequence of register writes is there
<azonenberg> 3
<azonenberg> but it's repeated for each SLR
<azonenberg> the {inst, inst, inst} notation indicates the JTAG IR for each of the three SLRs
<azonenberg> I conjecture, but am afraid to test, that you could do this faster
<azonenberg> by doing {CFG_IN, CFG_IN, CFG_IN} and broadcasting the bitstream to each chip
<azonenberg> each die*
<azonenberg> Rather than {CFG_IN, BYPASS, BYPASS} etc
<azonenberg> And well, it's not 9x as long
<azonenberg> it's 3x as much data, but then sent 3x redundantly
<azonenberg> 9x total time but 3x is overhead and 3x is actually there being more data to send
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<azonenberg> So basically the overall flow to configure a vu9p is:
<azonenberg> * broadcast JPROGRAM to all three SLRs
<azonenberg> Wait 100 ms, send 10K dummy clocks
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<azonenberg> Load CFG_IN to leftmost SLR, spam the bitstream to it
<azonenberg> Repeat for middle SLR
<azonenberg> Repeat for right SLR
<azonenberg> Load CFG_IN to middle SLR (master if memory serves me right), send CMD START;DESYNC
<azonenberg> Load CFG_IN to left SLR, send START;DESYNC
<azonenberg> Go to idle, send 100K dummy clocks
<azonenberg> Broadcast JSTART to all three SLRs
<azonenberg> send 2K dummy clocks, verify chip booted correctly
<eduardo_> azonenberg: you might want to point @maxslug at twitter at your problem
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<mithro> Morning!
<mithro> tinyfpga: can you send me an email at me@mith.ro and I will get an Arty in the mail for you.
<mithro> tinyfpga: I'll also include some of Rohit's adapter boards for dual-pmod to umti if I can figure out what I've done with them
<mithro> daveshah: morning?
<daveshah> mithro: Hi
<mithro> daveshah: So, I need to reintergrate your Verilog->XML changes now the Makefile stuff is almost finished
<mithro> daveshah: I'd love some feedback on https://github.com/SymbiFlow/symbiflow-arch-defs/pull/56 too
<mithro> daveshah: Getting close to being able to type "make" in the top level directory and have it do things :-P
<daveshah> mithro: I will look through it now. I started reintegration the XML generation stuff
<mithro> daveshah: oh cool
<daveshah> mithro: I need to add a make rule, I think to your deps makefile, to call the XML gen stuff
<mithro> daveshah: BTW You seem to be good at knocking out stuff quickly -- I need a Python script which does the same thing as https://github.com/mithro/symbiflow-arch-defs/blob/makefile-rework/common/xml/xmlsort.xsl but also does "deduping" IE two nodes are identical only one should be added
<mithro> daveshah: Yes, that is correct
<daveshah> mithro: would it be OK to run the make rule whenever *.sim.v exists but *.pb_type.xml doesn't or is out of date (excluding Ntemplate)
<mithro> daveshah: BTW I already have verilog deps generation here -> https://github.com/mithro/symbiflow-arch-defs/blob/makefile-rework/common/make/deps.mk#L176-L197
<mithro> daveshah: I think it should depend on the "$(call ALL,<verilogfile>)" target?
<daveshah> mithro: yes, that sounds good. BTW you can use yosys -E to make a dependency file IIRC
<mithro> daveshah: Oh cool - didn't know that
<mithro> daveshah: Not sure how that would work with the files being missing at the time?
<daveshah> mithro: Yes, you're right, it needs to open the files
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<daveshah> mithro: I left a couple of comments on the PR.
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<daveshah> mithro: Interesting, that's how timing data on the iCE40 is output by iCEcube - and hence how Clifford documented the iCE40 timing for icetime
<mithro> daveshah: It seems a pretty standard format?
<daveshah> mithro: Yes, it must be
<daveshah> mithro: Are you thinking about using a SDF file for the VPR XML generation, instead of Verilog timings? It looks easy enough to parse (we can even reuse the parser code from icestorm)
<mithro> daveshah: kind
<mithro> Kinda
<daveshah> Yes - I've been meaning to look at OpenTimer too. I think theoretically icetime can work with it, but I don't know if anyone ever tried
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<unixb0y> mithro: How's it going with X-Ray?
<mithro> unixb0y: More slowly then I would like
<unixb0y> I'm going to try to dig a bit deeper into the project as soon as my exams are over!
<unixb0y> Oh why is that?
<mithro> unixb0y: I spent a lot of the weekend fighting with Make
<unixb0y> I saw the commit ;)
<unixb0y> Well, now you figured it out!
<unixb0y> C'ya later!
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<daveshah> mithro: I have started a PR to your branch with some initial reintegration of the XML generation stuff
<mithro> daveshah: Cool
<mithro> daveshah: I got distracted by fixing some docs in VPR
<daveshah> But I still need to get it working in conjunction with the verilog deps stuff.
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<mithro> daveshah: Let me look at it
<daveshah> Also, we do need to get your Travis pr for yosys merged I think before we can get builds working with CI again
<azonenberg_work> Per twitter thread with Yannick
<azonenberg_work> It looks like I was wrong
<azonenberg_work> I think i'm parsing the .bit file incorrectly and it's not O(n^2)
<azonenberg_work> i think the .bit has more data after the DESYNC command
<azonenberg_work> Need to investigate more when i get home
<rqou> anybody want to try guessing how this works? (azonenberg you're ineligible :P ) https://twitter.com/rqou_/status/968190732572897280
<awygle> rqou: webmidi
<awygle> err no, CDC-ECM+rndis
<rqou> nope
<rqou> arguably even worse and hackier :P
<rqou> CDC-ECM+rndis was my old idea
<pie_> what do those even mean
<awygle> "remote network driver interface specification" iirc
<rqou> yeah, it's even hackier than that
<rqou> azonenberg thinks i shouldn't deploy it :P
<awygle> and "communications device class - ethernet control module"
<awygle> not to be confused with cipher block chaining which i always mix up with it
<awygle> my refactoring of this code took it from 70 MB/s to 3 MB/s... must be Monday
<pie_> yeah i was like cipher dlock chaining
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<pie_> rqou, does it involve dns queries
<pie_> man i havent the faintest clue what you could have come up with but i keep wanting to guess xD
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<pie_> s/dns queries/dns abuse/
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<rqou> no, no dns involved
<rqou> the hack i have in mind doesn't involve the network stack
<rqou> it's a very very specific (and very wtf) usb device
<awygle> writing C#, python, and verilog in the same day has me writing "foreach byte b in array begin" which isn't valid in any of the three
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<daveshah> Braille output devices or something of that level of obscurity?
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<whitequark> oh
<whitequark> simpler
<whitequark> just an USB sound card
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<rqou> nope, sound cards have permission prompts still
<rqou> and afaict the APIs to select a specific output device are still missing
<whitequark> you can definitely play something without a permission prompt.
<rqou> yes, but afaict you also can't select a specific output device
<whitequark> so what? just blast it over all existing ones
<rqou> will it?
<rqou> i thought you will be at the mercy of the system mixer settings
<whitequark> sure
<whitequark> so?
<rqou> not as good a plug-and-play experience as my current idea
<whitequark> rqou: then, printer.
<rqou> lolol
<whitequark> except I wouldn't call that "plug and play" lol
<rqou> i did think about that too
<rqou> but you can't automatically initiate a print from JS
<rqou> the LUFA guy did make a usb printer bootloader though (you would print an intel hex file to update firmware)
<whitequark> the gamepad API doesn't support feedback
<rqou> no, the idea was that you would send data to the device by playing sounds
<rqou> and the device would send data back by pressing buttons
<whitequark> >at the mercy of system mixer settings
<rqou> the one i'm thinking of isn't as convoluted
<rqou> it's just a lot more obscure
<whitequark> hmmmm
<whitequark> is this like "theoretically supported in the standard" or more like "i actually know this is decently portable"?
<rqou> it's also a major major abuse of the intended use case
<whitequark> because if it's the former then you could only mean one thing
<rqou> already implemented in chrome and on track to be implemented in FF (currently pref-ed off)
<rqou> not webusb obviously
<whitequark> is it supported in firefox nightly?
<rqou> it's already in releases but behind a pref
<rqou> so probably enabled in nightly?
<whitequark> FIDO U2F?
<rqou> ding ding ding ding
<rqou> you're winner!
<rqou> :P
<rqou> wow, very good
<whitequark> I was thinking about smart cards first because that's in the list of USB device classes
<whitequark> but that must be a cross-platform nightmare
<rqou> yup, exact same thought process here
<whitequark> however... what's like a smart card but without the nightmare?
<rqou> _exact_ same thought process here
<rqou> afaict you can smuggle "output" data in the u2f keyhandle, and "input" data in the returned signature
<rqou> and there's no permission prompts or ratelimits on this api
<rqou> (as long as you don't request attestation, which you don't need anyways)
<rqou> and it runs over usb hid
<rqou> if you have more spare time than me, try testing this in reality?
<whitequark> nah
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