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<kc8apf> I've reached the point in writing docs where I need register descriptions. Are there any neat tools for generating these from a markup language? A tool that will generate an SVG would be helpful.
<cr1901_modern> Yes, there are tools. Regrettably I don't remember them. I think the wavedrom dev did one of those "register generators" though
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<rqou> f*cking sign errors when trying to math
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<rqou> wow LaTeX is f*cking useless
<rqou> i can print preview from jupyter and everything works
<rqou> use latex to export and it doesn't line wrap
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<pie_> i hope there will be footage of the core splashdown/crash of the falcon heavy core
<jn> footage of the ...
<jn> ...
<jn> ... core dump :P
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<pie_> :P
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<kc8apf> cr1901_modern: someone else pointed me at wavedrom too. Need to see if I can tie that into Sphinx
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<qu1j0t3> pie_: https://twitter.com/andreymokhov/status/961191550532378626 ["After yesterday's exciting SpaceX launch it feels like the right time to share my recent project on formal verification of spacecraft control programs"]
<pie_> oh hey...
<pie_> qu1j0t3, has this come up in dependent yet?
<qu1j0t3> not to my knowledge
<qu1j0t3> you can break it, rookie
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<eduardo__> qu1j0t3: How did you find your way into this FPGA hacker forum ? your seem to be an academic.
* qu1j0t3 is not an academic
<qu1j0t3> in fact i've never set foot in a uni except to browse their libraries, buy books at fundraising sales, or attend very rare meetups
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<X-Scale> qu1j0t3: you haven't missed much, as the core of knowledge is now on the internet.
<qu1j0t3> that will be more true once we have proper public access to the last 1000 years of published research, but sure
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<cyrozap> kc8apf: A while back I made a list of tools to meet a similar need of mine--let me see if I can find it...
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<rqou> btw hey azonenberg azonenberg_work you should rebase your yosys
<rqou> i made a master_fixed branch that should have fewer issues
<cyrozap> kc8apf: Here's where I asked about it: https://irclog.whitequark.org/~h~openfpga/2017-11-11#20522782
<kc8apf> cyrozap: thanks
<awygle> i remember that inquiry. we came up with ~nothing lol
<kc8apf> I've got a few ideas to try out
<rqou> lol yeah
<rqou> i've seen ad-hoc hacks involving perl or yaml or whatever
<rqou> or xml
<awygle> i have a broad interest in like, a useful way to specify IP core interfaces
<kc8apf> If nothing else, wavedrom has logic for making pretty register diagrams in SVG
<awygle> to the level of detail you actually need (# of pipeline delays, what is synchronous to what, valid input and output spaces....)
<kc8apf> awygle: IP-XACT seems to be the way to go for that
<awygle> IP-XACT seems bad but possibly as good as it gets
<kc8apf> XML is never a good answer
<kc8apf> from a syntax standpoint, SystemRDL reads better. Haven't looked closely enough to see if it has all the necessary details though
<awygle> i have a hard time not seeing the sheer number of Accellera standards as just fire and motion
<kc8apf> similar to other standards orgs: member contributes a spec, it gets published
<kc8apf> adoption isn't really their concern
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<kc8apf> Saw the exact same thing happening in Open Compute
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<awygle> i am curious about what typical practice is for "real" FPGA/ASIC companies
<awygle> as opposed to hobbyists
<awygle> i should make some friends in that area i guess
<kc8apf> I've mostly seen ad-hoc systems built out of perl, TCL, or worse
<rqou> ^
<kc8apf> I know in 2009, Intel was hand-writing their register documentation.
<awygle> sure but ad hoc systems to do what? that's what's interesting. what features are they building, and what features aren't they building but would if they had the time
<kc8apf> best I've seen is generating verilog and C headers so HW and SW don't get out of sync
<sorear> can't go wrong with php generating verilog
<kc8apf> maybe a BDSL
<kc8apf> err BSDL
<rqou> "best" I've seen is perl (not "use strict" compatible) generating xml for framemaker
<kc8apf> ok, yeah. I saw that at Apple
<rqou> mine was at broadcom
<rqou> when i needed to touch it, i immediately dumped all the data from perl into json and ran away from the perl as fast as possible
<rqou> i personally have written a DSL that took in yaml definitions of structs with possible VLAs (no bitfields iirc) and outputted either C (with appropriate forward declarations) or javascript
<rqou> but this _sucked_ to use because the yaml was too verbose
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<cyrozap> kc8apf: Here's one of the ones I came up with in that conversation a few months ago: https://irclog.whitequark.org/~h~openfpga/2017-11-12#20527285
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<awygle> https://www.makerchip.com/ huh, this is interesting
<rqou> apparently i buy the same milk tea so often that i now trigger speculative execution. exploitation for fun and profit will be left as an exercise for the reader :P
<qu1j0t3> lol