<tinyfpga>
awygle: I found that presentation online, not necessarily specific to ECP5, but it’s the most detail I’ve seen on the generic Lattice FPGA architecture
<awygle>
tinyfpga: oh yeah very useful
<Xark>
tinyfpga: Hello there! :)
<awygle>
gotta love the official presentation having a bunch of "this is magic" "i don't know this" "this is cumbersome and difficult to learn"
<awygle>
huh, comparing the datasheets it does look like the XO2 and the ECP5 are ~the same architecture. PFU diagram is the same and EBRs are 18kb on ECP5 and 9kb on XO2
<tinyfpga>
awygle: make sure you have the Lattice diamond tools. Build a project using the ECP5 FPGA...could be anything. Then find the ncd2ncl and ncl2ncd files
<sorear>
is there a nice list somewhere of the materially different FPGA architectures? does lattice have more than two?
<awygle>
tinyfpga: i've got Diamond, i've used the ECP5s before :)
<awygle>
that's why i'm interested in helping RE them, i have both past and future projects with them
<tinyfpga>
awygle: run ncd2ncl on the inout NCD file of the bitstream generation step
* Xark
is goofing around working to get VGA text-mode on TinyFPGA Computer Project Board...
<awygle>
tinyfpga: are you targeting a specific part?
<tinyfpga>
awygle: the ncl format is really; really awesome
<tinyfpga>
LFE5U-25 285
<tinyfpga>
Xark: yay!
<Xark>
tinyfpga: Hey, is your newer TinyFPGA BX board pin compatible with the B2 one (for use in CPB)?
<Xark>
tinyfpga: BTW, awesome BGA "hack". :)
<tinyfpga>
Xark: it’s not exactly pin compatible
<tinyfpga>
Xark: I moved the 1.2v off the outer pins and put another ground their instead
<tinyfpga>
Xark: and all the outer pins are dedicated user io pins except for power. None of them are shared with spi, usb, or clock
<tinyfpga>
Xark: those pins and additional user IO are moved to surface mount headers on in bottom
<Xark>
tinyfpga: Hmm, I see. Oh well, I'll still likely get one. :)
<tinyfpga>
Xark: I will probably make another version of the computer board for the BX...will be able to have dedicated SPI RAM, SD card, and SPI Flash connections due to the increased number of IOs
<tinyfpga>
Xark: and more bits for VGA color
<awygle>
tinyfpga: did you have DLL problems with running ncd2ncl?
<tinyfpga>
awygle: it just worked for me
<awygle>
tinyfpga: did you run it from CMD?
<tinyfpga>
awygle: yes
<Xark>
tinyfpga: Excellent! :D
<tinyfpga>
awygle: maybe try to track down missing DLL via depends.exe
<awygle>
tinyfpga: *i* found them, it's just ncd2ncl that can't :-P
<awygle>
I can fix it just wondered if you had the same issue
<tinyfpga>
awygle: I was also running the whole flow from a BAT file
<tinyfpga>
awygle: from Verilog to bitmap file
<tinyfpga>
awygle: I did that in the same console I ran ncd2ncl, maybe one of the Lattice tools in that flow was setting up some paths
<awygle>
ah probably
<awygle>
okay, i have it running
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<awygle>
this is fun to play with. even without approaching it systematically
<mithro>
I think I have almost dug myself out of this makefile mess :-/
<tinyfpga>
awygle: yes...it’s pretty cool. The ncl is powerful. Much easier way to extract connectivity information and fuzz the bitstream
<mithro>
Hey tinyfpga!
<mithro>
tinyfpga: daveshah has mostly got verilog -> vtr XML working
<awygle>
tinyfpga: eventually we'll have to figure out the actual .bit file, surely? (after we've uncovered the structure with the ncl files0
<tinyfpga>
mithro: hey! That’s great news
<tinyfpga>
mithro: I have all weekend finally...should be able to get more down
<tinyfpga>
mithro: spent more time on the bootloader stuff than I expected
<tinyfpga>
mithro: might as well send me an arty Yo get the bootloader working on it XD
<tinyfpga>
awygle: Clifford has a script that correlates features to bit locations
<awygle>
interesting. well i'll look at your scripts tomorrow - time for bed
<tinyfpga>
awygle: the ncl file corresponds very closely to stuff on the bitstream...we will generate many different designs in NCL and correlate to the generated bitstream
<awygle>
oh i understand now. i had the directionality backwards.
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<rqou>
anyone here understand magnetics/transformers very well?
<rqou>
i have a problem that i've been stuck on for hours and making no progress
<rqou>
awygle
<rqou>
?
<awygle>
rqou: I will look at it and see if I can suggest a useful thing in <5 minutes, since I do need to sleep
<rqou>
in the problem, i am given a three-legged transformer in the "parallel" arrangement
<rqou>
ie three sets of turns around three "posts" that are joined at the top and the bottom
<rqou>
except for some reason this transformer is gapped on the three "posts" with an identical gap on each
<rqou>
two sine waves are applied to two of the ports
<sorear>
gapping is a pretty normal thing
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<rqou>
the third port has a resistor
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<rqou>
and the problem asks to determine the amplitude of the currents in terms of "V1, V2, N1, N2, and omega"
<rqou>
note that N3 is _not_ involved
<rqou>
and no matter what I do i can't make N3 go away
<sorear>
what's a N3
<rqou>
the number of turns for the third set of turns
<rqou>
which is connected to the resistor
<rqou>
intuitively it seems like eliminating N3 should be possible, but no matter what I do it doesn't actually work
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<rqou>
azonenberg are you good with magnetics?
<azonenberg>
Nope
<rqou>
ugh
<sorear>
what's driving the transformer?
<rqou>
an ideal voltage source
<azonenberg>
Welp, one step closer to my dream network setup
<azonenberg>
vmware box in DMZ is now serving VNC right out of the hypervisor (not a vnc server in the app)
<azonenberg>
Which my main rig connects to
<azonenberg>
i think i'm close to being able to semi-airgap my main workstation (no general purpose inbound or outbound access, only 5900 to DMZ plus 443 to package mirror
<rqou>
alright, i officially give up on this problem
<rqou>
i've spent 4+ hours on it and made zero progress whatsoever
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<cr1901_modern>
rqou: You mind making a scan of the problem and posting a link? I'm curious to see.
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