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<azonenberg_work> mithro: the bits marked ECC in the HCLK tiles
<azonenberg_work> what do those do?
<azonenberg_work> is this actually bitstream forward error correction?
<azonenberg_work> for FRAME_ECC2?
<azonenberg_work> FRAME_ECCE2*
<felix_> those are the bits for the error detection/correction
<azonenberg_work> yeah, i forgot that 7 series had full FEC for the bitstream
<azonenberg_work> instead of just CRC
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<knielsen> Hi, it was cool talking to you all at the FPGA assembly @ 34c3
<knielsen> I updated my ICE40 floorplan viewer so now connections in IO tiles are also drawn (it was missing until now)
<zino> Any published FPGA-related talks?
<pointfree> zino: From 34c3 or in general?
<zino> 34c3, but feel free to recommend others if you have them. :)
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