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<
rqou >
whee, time to actually start studying for my final tomorrow
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<
cr1901_modern >
5 years since I last took a final...
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<
pie_ >
<clever> pie_: this is one of the more crazy things ive done, this boots nixos, under xen, under qemu
02:02
* pie_
mumbles about build systems at rqou
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<
awygle >
damn, the LNA on my downconverter has been EOL'd
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<
cyrozap >
pointfree: I pushed the macrocell model to my psoc-bitstream-parsing-tools repo. I haven't pushed the PLD model yet because I'm still trying to get it to work.
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<
pointfree >
cyrozap: cool!
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<
cyrozap >
The plot thickens: For some reason, when I synthesize just the PLD model Verilog module (without the UDB block), the output says that some of the macrocell "selin" and "selout" pins aren't being used, which is odd because they're supposed to be in a chain that goes all the way through the PLD module.
07:21
<
cyrozap >
So, either Yosys has a bug, or I don't understand Verilog very well.
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<
cyrozap >
I'm betting on the latter :P
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cyrozap >
pointfree: I pushed the non-functional PLD code.
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learnerd >
are there any fpga manufacturers that offer an open source toolchain?
16:52
<
jn__ >
i don't think so. but there are open source toolchains for FPGAs (lattice iCE40, most notably)
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<
azonenberg >
learnerd: None that are officially vendor supported, no
16:55
<
azonenberg >
I would love if our toolchain for silego greenpak parts ended up like that eventually
16:55
<
azonenberg >
The vendor is aware of our project and has been very helpful
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<
azonenberg >
and has gone as far as tweeting links to my tools from their official company account
16:55
<
azonenberg >
But doesn't ship our tool or anything like that
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<
learnerd >
ok, thanks for the info
17:00
<
awygle >
Has anyone been following the Microsemi RISC-V stuff? This Freedom Unleashed sounds.... Extreme
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<
awygle >
Err, hi-five unleashed rather
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<
jn__ >
extreme in which way?
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<
awygle >
It has "five 64-bit RISC-V cores running at 1.5 GHz plus" and a PolarFire FPGA (12.7G transceivers)
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<
awygle >
DDR4, GigE, etc. Giving it the same name as an arduino-compatible seems very strange
17:04
<
awygle >
I was expecting a Freedom E300 with an Igloo or something
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<
jn__ >
i think the important part of the branding is "Unleashed", here
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<
jn__ >
"Freedom Unleashed" is the name of sifive's "linux-capable" cores
17:05
<
awygle >
Yeah I guess that means their Linux capable line. The FPGA is still much bigger than I expected tho
17:06
<
azonenberg >
Sounds like a Zynq competitor
17:06
<
azonenberg >
But until their toolchain catches up it's dead to me
17:06
<
azonenberg >
i'm not even going to bother doing bitstream RE if the vendor tools are so broken that i cant run a blinky on my own computer
17:07
<
awygle >
It looks more like somewhere between an Artix and a Kintex to me. No hard processor
17:07
<
azonenberg >
wait the five 64-bit cores are softcore??
17:07
<
jn__ >
azonenberg: no
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<
awygle >
No they're just external
17:07
<
azonenberg >
This is a SoC + FPGA board
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<
jn__ >
that's SiFive's hard IP
17:08
<
azonenberg >
Not a single board?
17:08
<
azonenberg >
not a single chip*
17:08
<
jn__ >
the fpga is effectively the southbridge on that board
17:08
<
jn__ >
more or less
17:09
<
awygle >
Seeing as you can't buy either the SoC or the FPGA yet I'd guess it's a ways out but still much more interesting than I expected
17:09
<
azonenberg >
Welp, heading out to the airport
17:09
<
azonenberg >
Be back online from the ferry / airport in a bit
17:10
<
awygle >
Enjoy your trip
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<
awygle >
I wonder how much Microsemi makes on software licensing
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<
rqou >
halp halp final exam cramming time
17:13
<
awygle >
They seem like they might be good "corporate partners" for this project, if we could offer them a leg up vs. Lattice et al
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<
cyrozap >
pointfree: Yeah, I saw it when it was pushed last year.
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<
rqou >
survived finals
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awygle >
rqou: congrats
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<
jn__ >
pie_: nice codegolf thread!
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