<azonenberg>
Sooo i think i found a Schottky that can handle the current i'm interested in
<azonenberg>
There's just one problem
<azonenberg>
30+ pF capacitance to ground :(
<azonenberg>
that cannot be good for signal integrity
<lain>
Z0 ~= sqrt(L/C) -> increase your L to keep it ~50 ohm? :D
<lain>
:P
<azonenberg>
Sounds like a great way to add loss, no?
<azonenberg>
i dont want to attenuate the signal either :p
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<lain>
hm
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<lain>
it depends on the Q of the schottky, I think
<lain>
you won't see any higher resistive losses, as long as the conductors remain the same size
<lain>
dielectric loss shouldn't change because the dielectric doesn't change
<lain>
you can increase the inductance to compensate for higher capacitance by making a hole in the ground plane under the relevant component, but you'd need a true 3d field solver to figure out the ideal size
<lain>
this is commonly done to compensate for the increased stray capacitance of AC coupling capacitors in multi-gbit interfaces
<lain>
but, I don't know that it's that big of a deal :D
<lain>
or maybe I'm talking nonsense
<lain>
it's been a while since I had to concern myself with loss figures
<lain>
hrm.
<azonenberg>
@_@
<azonenberg>
yeah...
<azonenberg>
I think i'm just gonna pick up that diode and drop it on th eboard
<azonenberg>
then do some eye measurements :p
<lain>
:D
<azonenberg>
worst case if i dont get the b/w the fpga is capable of
<azonenberg>
i can always respin the io board in the future
<lain>
plus I still think you'll need to buffer very fast signals with a fet at the probe tip
<lain>
so you'll get a nice fat signal anyway if you do that :D
<azonenberg>
I'm topping out at 800 MSa/s
<azonenberg>
if not clock synced that means circa 200 Mbps max i think
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<cr1901_modern>
lain: Why the fet? Impedance conversion?
<azonenberg>
and yes i expect i will need an active probe for really fast stuff
<azonenberg>
but for what i'm doing here my hope is that i ca nget by without it
<azonenberg>
i'm probing PCB traces, not IC dies
<azonenberg>
internal nets on IC dies*
<rqou>
the "clean my room" project is swap thrashing again
<rqou>
i should garbage collect :P
<fpgacraft2>
<nmesisgeek> lol, i actually made progress cleaning up my desk and the garage
<fpgacraft2>
<nmesisgeek> cant wait till it gets a bit warmer so its more comfy to work out there
<fpgacraft2>
<nmesisgeek> that's one of the things slowing me down
<rqou>
i''ve been working on "clean my room" for a week now
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<lain>
cr1901_modern: fet active probe is to prevent loading the device under test
<lain>
nats`: I don't mean add an actual inductor, but add some inductance by e.g. a ground cutout around the device that is adding the capacitance
<nats`>
it'll still behave as a filter
<nats`>
it can help but I would select better component in first place
<lain>
hm, I thought it would just introduce phase delay due to the distributed LC?
<nats`>
you'll have a phase delay because it's a low pass filter so your edge will be slowest
<nats`>
don't know the term in english but it'll not be totally vertical anymore
<nats`>
but if value are really low we can use that trick
<nats`>
I think using a redriver coul be a good thing
<nats`>
and you can put it before the protection
<nats`>
if it dies it's not that bad
<nats`>
just change the SOT23
<lain>
nats`: I'm not sure that's correct
<lain>
it should still be in LC mode operation, should it not?
<nats`>
which part ?
<nats`>
I'm not sure where you plan to add the equivalent serie L
<lain>
as I said, a ground plane cutout under the part
<nats`>
so you add serial L of few nH
<lain>
this is common for example in multi-gbit interfaces, doing a cutout under the AC coupling capacitors to offset the additional stray capacitance from their component pads
<nats`>
(I wouldn't add a cutout)
<lain>
but you need a 3d field solver to determine the appropriate size
<nats`>
ah yes that one but that's only to reduce capacitance of pad
<nats`>
here the problem is the diode behavior itself
<lain>
hm true, this is different yeah
<lain>
but, hm..
<lain>
right
<lain>
this is lumped element region
<nats`>
yep
<nats`>
it's basically a EPC of diode
<nats`>
equivalent parallel diode
<nats`>
capacitor
<nats`>
but the easy solution is to get protection device for USB3
<nats`>
they are fast protecting diode with stuff like few pF
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<ZipCPU>
eduardo_: That you? I didn't realize that any of the icoBoard team had a presence on any of these channels.
<nats`>
eduardo_ I'm more wondering about where I put my module in icestudio tree :)
<nats`>
i'm slowly discovering it :)
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<eduardo_>
nats: sorry, cant help with iceStudio code
<eduardo_>
clifford and I am here from time to time.
<balrog>
drag someone from icestudio into here I guess :)
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<lain>
azonenberg: so I just noticed something interesting
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<lain>
azonenberg: ds181 artix7 dc/switching has new devices, the 12T and 25T, both have same static power, and are surely the same as spartan7 ... but 15T is still higher static power shared by 35T and 50T o_O
<azonenberg>
Yes
<azonenberg>
the 15 is a fused 35/50
<azonenberg>
Meaning you are better off using a 25 than a 15 if you are trying to minimize power
<azonenberg>
spartan7 i think has a 6k cell device as well iirc
<azonenberg>
forget if thats a custom die or a fused 12t
<balrog>
azonenberg: they finally released spartan 7?
<azonenberg>
announced
<azonenberg>
not for sale yet
<balrog>
it was announced a year ago -.-
<azonenberg>
basically they forked the 7 series low end line into s7 for s6 lx
<azonenberg>
and a7 for s6 lxt
<azonenberg>
then kintex replaces low-end virtex and high-end virtex remains virtex
<balrog>
artix-7 was available way earlier
<azonenberg>
yes
<azonenberg>
My guess is, they held off on the no-gtp version to see if there was market demand
<azonenberg>
and a lot of people doing designs without gtps
<balrog>
people were sticking to spartan-6 and using ISE :(
<nats`>
S6 willstay for long
<nats`>
better static power
<nats`>
and IO wise more interesting than S7
<nats`>
for the same pacakge you have more PIN on S6 than S7
<lain>
azonenberg: yeah I suspect S7 6k size is fused 12T
<nats`>
usable pin I mean
<lain>
actually iirc I did verify static power is same
<nats`>
uhhmmm IIRC S6 is a little beter than S7
<azonenberg>
Yes
<azonenberg>
7 series wins for dynamic in some cases
<azonenberg>
but for static s6 wins massively
<azonenberg>
7 series leaks
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<azonenberg>
lain, rqou: So hmm
<azonenberg>
If i were to bump my series resistor up to say 30 ohms
<azonenberg>
instead of 10
<azonenberg>
that would cut peak fault current down to 400 mA
<azonenberg>
It would act as a series terminator if i'm driving a signal
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<nats`>
shit I thought artix 7 15T was pin 2 pin compatible up to 50T
<nats`>
but apparently nop
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<lain>
hm? it is in fgg484
<nats`>
need to check but they make a difference between 15-35T and 50T in FGG484
<lain>
yes
<lain>
just the presence of bank 13 afaik
<nats`>
how much soldepaste do you put on those pad ?
<nats`>
in their doc they say 0.5 and SMask 0.6
<nats`>
but don't say about solderpaste
<lain>
I follow IPC guidelines
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<carl0s>
nats`, still want to know where to place your module to see it on the iceStudio component tree?
<nats`>
hello I'm interested yes but I'm going to bed :)
<nats`>
it's almost 1 o clock
<nats`>
can we chat tomorrow or by email ?
<carl0s>
oh, ok, 17.37 here in méxico
<carl0s>
yes, np
<nats`>
hehe :)
<nats`>
I'm in france :)
<nats`>
see ya later :)
<carl0s>
cya
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