azonenberg_work has quit [Ping timeout: 260 seconds]
<lain>
fast square wave edges generate a lot of harmonics, that may be a reason they are singled out, but I dunno
<sorear>
analog FM receivers generate square waves too
<lain>
semi-related, we were picking up some interesting signals the other day, they were popping up all over the 200-300 MHz region and some other regions. they presented as a narrow carrier hopping up and down across a range of maybe 9-15 kHz (it varied by location), as measured by a small pile of rtl-sdrs
qu1j0t3 has quit [Quit: WeeChat 0.4.3]
<awygle>
lain: FHSS or did they have a longer dwell time?
<lain>
two things were particularly notable: 1/ the signal was hopping in roughly a sine wave pattern over time, see waterfall: https://i.imgur.com/4UxNQZB.png , and 2/ the fact that this was mostly (or entirely?) within the military air bands
m_w has quit [Quit: Leaving]
<lain>
turns out it was our Avermedia HDMI recorder (a little hdmi pass-thru box with a linux machine inside, can record hdmi stuff)
<awygle>
huh, cool
* awygle
has never recorded anything useful with his rtlsdr
<lain>
we took it apart but didn't see any really obvious causes. best guess is the component video input was idly hopping between sync frequencies to try to lock onto something, even though no sync signal was present (we never used the component inputs)
<lain>
and for whatever reason it was radiating /heavily/
<awygle>
sounds like a job for Near Field Probe Man
<lain>
I'd be surprised if this passed FCC, though it claims to
<lain>
ehehe
<lain>
yeah
<lain>
one of these days we'll find the time, I'm really curious
<awygle>
i always forget what the mask actually is but isn't it pretty wimpy at 300 MHz?
<lain>
lacking a near-field probe, I thought it might be fun to selectively freezer-spray the components and oscillators, watching for frequency shifts in the radiated noise
<awygle>
lol
<lain>
but we didn't wind up doing that either :P
* awygle
has a story about a cold SPI memory
<lain>
:o
<awygle>
i got a call one day (i think after i'd quit my job?). "why does your radio lose lock at -15 degrees C?"
<lain>
o.o
<awygle>
my thoughts exactly
<awygle>
so i go in and they've got it in the thermal chamber and we're bringing it down. -10, works great. -15, WOAH where'd the radio go?? -20 oh there it is
<lain>
oh that's even weirder
<awygle>
cutting the debugging short a bit, the transceiver shared a SPI bus with a memory chip
<awygle>
when the temperature dropped into that band the memory went _crazy_
<awygle>
started spewing all kinds of garbage onto the MISO line
<lain>
O_O
<sorear>
but it works fine at -20C?
<awygle>
if i remember right, it turned out that it was being initialized wrong, and so it was in an invalid state that _almost_ worked, but got pushed into crazytown under certain amounts of frequency drift
<awygle>
or something like that
<awygle>
i remember it wasn't my fault and it was fixed in software
<lain>
hah
<lain>
that's awesome
<awygle>
yeah that's the weirdest bug i've ever hit lol
<awygle>
TVAC testing produces all kinds of weirdness though
<awygle>
not only is it a very stressful thermal environment but also it's a horrible RF/EMI environment
<awygle>
heaters and pumps switching on and off at semi-random
<awygle>
and iirc we screwed up the grounding really badly the first time and got massive ground loops that ruined everything
qu1j0t3 has joined ##openfpga
<awygle>
because our coax passthrough's shield was terminated to the bell of the chamber or something
<qu1j0t3>
b/b 17
<sgstair>
hee
<lain>
we have an interesting thing on the power line here, we're seeing a weird sort of... I guess it's sort of a half-wave-rectified triangle wave? on top of the mains sine. it's a few volts peak to peak when it's around, but its actual intensity varies
<lain>
it comes and goes
<lain>
we've got an oscilloscope just sitting here plotting the mains waveform and an FFT of it, and a little nanopi neo2 connected over usb which is taking scope captures every 10 seconds
<lain>
we first noticed it because our appliances /buzzed/ sometimes. well, some of them, anyway. an audio spectrometer app on android says the buzzing is around 11-12 kHz, and sure enough the FFT of the mains noise (which correlates with the buzzing sound) shows peaks typically at around 11 and 23 khz
<awygle>
oo that's fun
<awygle>
did you report it to your utility provider?
<lain>
we noticed it seemed to occur more often the colder it got, so we plotted the peak power in the frequencies of interest vs. local temperature, and sure enough it correlates very strongly
<lain>
awygle: not yet, but I think we're almost done having fun with it :P
<lain>
I do kind of want to run around with a big loop antenna and see if I can find an origin location
<lain>
but we looked around and it looks like our transformer is shared only with our neighbors, so it's likely some sort of heater at their place
<lain>
I highly doubt it's something on the HV line feeding the transformer
<lain>
another fascinating thing (which is really fun to watch on the oscilloscope in realtime) is our inverter microwave dumps noise all over the like 15-50 kHz band or so, but if the 23 khz anomaly is present and strong enough, the inverter circuit seems to lock onto that and resonate
<lain>
you can see the noise floor rise up around it, then suddenly hug the 23khz mains noise and the microwave emits the most amazing audible buzzing :P
<lain>
it's pretty great.
<awygle>
woah, cool
<awygle>
i guess that makes sense
<lain>
I'm REALLY curious what the heck is doing it though. to generate several volts of peak-to-peak noise on a mains line can't be easy...
<azonenberg>
lain: re your HDMI thing
<lain>
I don't know what impedance I could use to model the transformer but I assume given the typical 100A service it's "pretty freakin' low"
<azonenberg>
is it possible it's spread spectrum emissions of the hdmi pixel clock?
noobineer has joined ##openfpga
<lain>
azonenberg: I assumed spread spectrum clocking would be a lower frequency oscillation mixed into the normal oscillator, rather than something hopping between discrete frequencies (though it's not totally clear from our analysis, it could be sliding quickly between frequencies)
<lain>
I would think such rapid frequency hopping would do more harm than good in terms of spreading the energy out over the spectrum, which spread spectrum is intended to do
<azonenberg>
spread spectrum normally is applying a fairly fast (kHz level) sine/triangle offset to the carrier
<azonenberg>
iirc
<lain>
innnteresting
<sgstair>
If you're discussing what I think you're talking about - in this case the frequency hopping period is about 1Hz
<lain>
(the offending hdmi thing is at sgstair's place)
<lain>
he has been POLLUTING THE AIRWAVES for YEARS :P
<sgstair>
extremely locally
<lain>
yeah only within a bubble of about... the dimensions of the apartment
<sgstair>
can't even pick it up from the parking lot :P
<lain>
yeah the walls seem to attenuate it fine
<lain>
you can pick it up in the walkway just outside the door, it fades quickly as you approach the stairs though
<lain>
have to be right against the window to get it out there
<lain>
anyway I'm not even sure how to approach the power company about this. I mean sure we can explain that sometimes our appliances buzz, but should I explain... that we attached a persistent logging system to the mains and then flipped all our breakers to make sure it wasn't us? :P
<sgstair>
the latter part is better left off in the first tier of support :3
<lain>
haha
<sgstair>
I dunno actually; not sure what to expect from them in terms of competence.
<lain>
need to just grab a PSE employee off the street and drag them over here :P
<lain>
my only experiencing talking with power companies directly, other than reporting outages, was two instances where it didn't take much understanding of electricity to grasp that Bad Things™ were happening
<lain>
once was a tree limb which, waving in the wind, would smack the live and neutral lines together (strung between two poles), causing a wonderful shower of sparks and a bang :3
<lain>
we sat and watched it for a while before calling to let them know the transformer was probably getting sad
<lain>
it was pretty small there, but it turned out we had a filtered power strip plugged into the same outlet we were measuring from, and unplugging that made the noise muuuuuch higher
<awygle>
PSE is pretty cool in my limited experience
<lain>
hmm... anyone know the legality of recording trunked radio comms? assume it's entirely unencrypted, NFM analog voice channels
azonenberg_work has joined ##openfpga
<lain>
I assume it's fine because it's broadcast publicly and stuff like broadcastify exists to stream things over the internet anyway, but I dunno
<sgstair>
I'm pretty sure that's legal, yeah. Gets touchy with cellphone signals and encrypted signals.
<lain>
kk
<lain>
related: the PSE peeps are so nice on their trunked radio system
<lain>
very polite
<lain>
this will be most fun during an outage
digshadow has joined ##openfpga
<awygle>
lmao nice
balrog has joined ##openfpga
unixb0y has quit [Ping timeout: 260 seconds]
soylentyellow has joined ##openfpga
unixb0y has joined ##openfpga
noobineer has quit [Ping timeout: 240 seconds]
balrog has quit [Ping timeout: 240 seconds]
balrog has joined ##openfpga
rohitksingh_work has joined ##openfpga
pie_ has quit [Ping timeout: 260 seconds]
pie_ has joined ##openfpga
<digshadow>
FYI in case anyone is interested, I'm documenting xc2000 bitstream format. Still very early on, but I've parsed out the frames and am starting to get LUT contents documented
<rqou>
wtf why?
<digshadow>
rqou: 2 main reasons
<digshadow>
1) we want to use it as an example for VPR, and someone also might do a more detailed writeup on xc2000 in general, so having the binary format would complement that nicely
<sorear>
how does that differ from the work that's already been done on xc2?
<digshadow>
2) the main reason is that I have a friend with an old peripheral he wants the schematic from
<digshadow>
sorear: ah? I was not aware someone did something
<digshadow>
link?
<azonenberg>
sorear, digshadow: i think ther'es confusion as to the part
<azonenberg>
xc2000 = ancient xilinx first-gen FPGA
<azonenberg>
xc2c = modern-ish 180nm xilinx product term cpld
<azonenberg>
the latter is what me and rqou were working on
<sorear>
ah.
<rqou>
document too many of these ancient parts and the us military is going to show up asking for help :P
<digshadow>
rqou: well when I'm starving and on the street, maybe that will be a godsend
<sorear>
as opposed to the other way around?
<cr1901_modern>
digshadow: I thought you said it was already documented (hence the tar you gave me)
<cr1901_modern>
xc2064 == first FPGA period. It comes in a 48-pin breadboard friendly DIP package :3
<digshadow>
cr1901_modern: those were old notes when I poked at it briefly
<digshadow>
this is more serious effort
<digshadow>
the git repo I have up now far surpasses those notes
<digshadow>
cr1901_modern: did you work on it at all?
<digshadow>
far surpasses => low bar
<cr1901_modern>
I only glanced at it, but was thinking of making a working blinky or similar my RC2018.4 project
<cr1901_modern>
I'm still undecided on what I want to do
Bike has quit [Quit: Lost terminal]
<cr1901_modern>
digshadow: What machine are you running the tools on?
<cr1901_modern>
Does Xilinx provide anything that targets the xc2064 that works on modern machines?
<azonenberg>
loool
<azonenberg>
the xc2064 was eol'd probably 20 years ago
<cr1901_modern>
azonenberg: I'm pretty sure xc2064 was EOL'd when spartan 3 was new
<cr1901_modern>
which makes me think there might be a legacy version w/ spartan3 support that still targets xc2xxxx
<azonenberg>
maaaybe
<azonenberg>
the toolchain for this predates ise
<azonenberg>
ise was not the original xilinx toolchain
<azonenberg>
there was a time when it was the new hotness like vivado is today
<rqou>
oh really?
<azonenberg>
i've used the old toolchain, i forget the name
<azonenberg>
for an xc4000 series part
<rqou>
i don't think i would ever call ISE "hotness"
<azonenberg>
because 'advanced computer hardware design' at rpi was stuck in the stone age
<rqou>
i got the impression ISE always sucked
<azonenberg>
a pci board with five 10k gate xc4000 parts
<rqou>
even in the ISE4 era
<azonenberg>
in a dec alpha
<azonenberg>
we did dev on a win98 box then ftp'd the bitstream over to the alpha to run our project
<azonenberg>
an ide hard drive controller
<sorear>
did the tools run on the Alpha or were they always x86-only
<sorear>
ah
<azonenberg>
i dont know if they had an alpha build
<azonenberg>
we didnt use it
<cr1901_modern>
your project was an ide hard drive controller?
<azonenberg>
Worse
<azonenberg>
they gave us vhdl for one
<azonenberg>
we had to finish it, and fix the bugs
<cr1901_modern>
... how old are you again?
<azonenberg>
this was in circa 2011
<rqou>
azonenberg is ancient :P
<rqou>
(no, not really)
<azonenberg>
the fpgas we were working on had date codes around the time my brother was born
<rqou>
oh btw berkeley has an xc4000 project on display somewhere from some class ages ago
<rqou>
but they're not currently in use
<azonenberg>
the second project for the class was a simple CPU
<pie_>
everything is only as advanced as as hard as you make it :PP
<azonenberg>
... with SCHEMATIC ENTRY
<azonenberg>
for some first-gen cyclone part iirc
<cr1901_modern>
My final fpga project was to make a (very academic) risc cpu. With no interrupts.
<cr1901_modern>
My final digital I project was a stopwatch.
<azonenberg>
cr1901_modern: my final project for ACHD was a 5-stage pipelined mips running C compiled with gcc
<azonenberg>
lol
<azonenberg>
On a pcb i designed and hand soldered
<azonenberg>
With a spartan6
<pie_>
pk you can stop showing off now :P
<azonenberg>
yes, i used an xc4000 and a spartan6 in the same class
<sorear>
hopefully, assuming the toolchain for the xc2000 still exists in machine readable form, it can be run in some easily-emulated environment like x86 DOS
<pie_>
i finally got the xilinx hardware server running
<cr1901_modern>
I still wouldn't want to go to rpi even if it seems their hardware courses are far superior
<pie_>
sorear, get that stuff up on archive.org
<pie_>
inb4 b&
<azonenberg>
cr1901_modern: well they have other problems too
<azonenberg>
in case you havent read the news
<cr1901_modern>
No, but did your president do something again?
<azonenberg>
lol i meant over the past few months in general
<azonenberg>
and years
<cr1901_modern>
No I can't say that I have read the news
<cr1901_modern>
azonenberg: I'm not sure I agree a full 5-stage pipeline mips from scratch is a good final project, or even a semester project. It's easy to get stuck in "find which control signal is failing to fire at the right time" hell.
<azonenberg>
cr1901_modern: well i had done pipelined cpus before
<azonenberg>
this was like round 2 or 3, a from scratch rewrite to fix some of the design mistakes i made in earlier ones
<cr1901_modern>
But the whole class each had to do their own impl?
<cr1901_modern>
Were they all doing round 2 or 3?
<awygle>
cr1901_modern: Hennessey and Patterson basically gives you the entire design iirc
<cr1901_modern>
You'll still end up playing a fun game of "which control signal is failing to fire at the right time"
<awygle>
although at Berkeley at least we didn't do the pcb or gcc bits
<rqou>
i assume you also took cs150?
<awygle>
check
<awygle>
I did not do the mips project but we did it in 61c
<rqou>
when i took it it was a risc-v project
<rqou>
it was also an experiment with combined lectures with ee149
<azonenberg>
cr1901_modern: lol no
<rqou>
after that, they decided that that would be too much material :P
<azonenberg>
everyone could do their own project
<azonenberg>
one team added an 8-bit scaled down ieee754 fpu to the schematic CPU (fpu in schematic sounds like torture)
<awygle>
149 was good
<azonenberg>
another did some kind of dsp something
<azonenberg>
i went with the mips
<rqou>
i never took 149
<rqou>
but a combined class is kinda a lot of material
<awygle>
State machines for days
<azonenberg>
my teammates were supposed to build me a cache, but they ended up falling flat on their face
<rqou>
one of the hardest problems in CS :P
<awygle>
I learned a lot about how not to do rf rangefinding :-P
<rqou>
er, is 149 the wrong class?
<rqou>
i was thinking of the asic design class
<awygle>
Embedded systems?
<awygle>
That's like 143 iirc
<awygle>
Which I did not take
<rqou>
no, that's microfab
<rqou>
the one i'm thinking of is _now_ called 146L
<rqou>
i don't remember if that's what it was before
<cr1901_modern>
My final verilog project was a VGA controller IP for the uni IP cores library. I don't think it ever was used though.
<rqou>
awygle: argh, i can't find the old retired asic course number
<rqou>
right as i graduated berkeley migrated most of their infra off of their old custom stuff
<rqou>
so all the old info is gone now
<rqou>
berkeley: really fancy school, really shitty information systems
digshadow has quit [Ping timeout: 260 seconds]
<azonenberg>
rqou: i wish i could have taken the 4000-level computer architecture course at rpi
<azonenberg>
the prof who taught it retired like the semester before i started
<rqou>
ugh, mutable state is hard
<rqou>
azonenberg: btw, we really need to do _something_ about XORs/TFFs
<rqou>
the largest counter that you can fit in an xc2c32a right now is only 14 bits which isn't enough to make the LEDs blink at a visible rate
<rqou>
more than that and you run out of p-terms
<azonenberg>
so, theres a couple of options
<azonenberg>
to start, we can do a custom techmap pass in yosys
<azonenberg>
use my existing RE-focused counter extraction
<azonenberg>
then techmap cr_count cells to chains of xors
<azonenberg>
But i think the better option is to do the tff extraction
openfpga-github has joined ##openfpga
<openfpga-github>
openfpga/master 3876f7d Robert Ou: xc2par: Bugfix: reset arrays when mapping the ZIA
openfpga-github has left ##openfpga [##openfpga]
<openfpga-github>
openfpga/master b2cb366 Robert Ou: xc2par: Fix bug where we try to swap to a site that cannot move
<openfpga-github>
openfpga/master d032b94 Robert Ou: xc2par: Work on chasing down some bugs in the min-conflicts logic
<openfpga-github>
[openfpga] rqou pushed 4 new commits to master: https://git.io/vx8wx
<azonenberg>
i forget if that made it to master
<azonenberg>
or if thats only in my branch
<rqou>
no
<azonenberg>
(which yes, needs to get rebased)
<rqou>
clifford thought it was to hacky
<rqou>
I ALREADY DID THAT
<rqou>
you never double-checked it
<azonenberg>
I'll look this weekend maybe
<azonenberg>
If i have time (yeah right)
openfpga-github has joined ##openfpga
openfpga-github has left ##openfpga [##openfpga]
<openfpga-github>
openfpga/master f464b8f Robert Ou: xc2par: If no choice is better, move somewhere random
<openfpga-github>
[openfpga] rqou pushed 1 new commit to master: https://git.io/vx8r0
<rqou>
ugh, there's a random other bit of nondeterminism somewhere in my code
openfpga-github has joined ##openfpga
openfpga-github has left ##openfpga [##openfpga]
<openfpga-github>
openfpga/master 4b7c17e Robert Ou: xc2par: Fix a new source of nondeterminism
<openfpga-github>
[openfpga] rqou pushed 1 new commit to master: https://git.io/vx8rx
pie_ has quit [Read error: Connection reset by peer]
rohitksingh_work has quit [Read error: Connection reset by peer]
Bike has joined ##openfpga
wpwrak has quit [Ping timeout: 264 seconds]
wpwrak has joined ##openfpga
pie_ has quit [Ping timeout: 256 seconds]
<mithro>
morning everyone!
<daveshah>
mithro: morning!
<mithro>
rqou: Congratulations on the first steps to making the coolrunner II a supported part!
<mithro>
hey daveshah - hope your exams went well!
<mithro>
daveshah: And your ready to do VPR hacking :-P
<daveshah>
yes went pretty OK in the end - last thing was a FPGA project demo today, fortunately went well as my processing block was running at the theoretical limit (memory bandwidth constrained)
<daveshah>
mithro: yes :D
<daveshah>
will look at the location and block attribute and parameter stuff
<mithro>
daveshah: Great!
<mithro>
daveshah: I think we need to come up with a decent definition of the difference between an attribute and parameter :-P
<daveshah>
mithro: Yes - arguable we only need attributes on tiles and locations. IMO parameters are strictly those specified in HDL
<mithro>
daveshah: What is the difference in your eyes?
<daveshah>
whereas attributes cover both HDL attributes and interbal config
<daveshah>
*internal
<daveshah>
based on how vendor flows AFAIK
<mithro>
daveshah: Dunno - I'm still very fuzzy on the difference - I think clifford has an opinion though and happy to go with whatever he says
pie_ has joined ##openfpga
<daveshah>
mithro: For now I think it will be best to stick with attributes only everywhere except where HDL is involved. I would say a parameter is something directly settable by a user whereas an attribute is more internal and would not normally be directly set by a user.
<mithro>
daveshah: SGTM - I don't hugely care what they are called :-P
pie_ has quit [Ping timeout: 276 seconds]
sunxi_fan has quit [Ping timeout: 256 seconds]
uovo has joined ##openfpga
oeuf has quit [Ping timeout: 264 seconds]
<kc8apf>
awygle: you're in the Seattle area? I'm flying in today.
<awygle>
kc8apf: I am indeed
<awygle>
What brings you to our fair - if soggy - city?
<kc8apf>
awygle: I'm up in Kirkland/Redmond ~twice a month. I'm always looking for a place to hang out between when my flight gets in on Friday and 3pm.
<awygle>
kc8apf: in point of fact, I live in downtown Redmond
<kc8apf>
digshadow-c: from that dump, looks like a byte order detection pattern and then a header. Doesn't quite look like a modern BIT header.
<kc8apf>
awygle: well, if you want to say hello, just let me know. I usually have free time.
<sgstair>
I'm also in Redmond, but tied up today.
<awygle>
sgstair: that's why you always leave a note
<awygle>
lain: you're local too, right? If you're on the east side maybe we can drag azonenberg off his island sometime :-P
noobineer has joined ##openfpga
ondrej2 has quit [Quit: Leaving]
<sgstair>
good luck with that, I have my hands full trying to drag lain away from the island :P
* awygle
starts printing East Side FPGA banners and merch
pie_ has joined ##openfpga
<sgstair>
East Side FPGA, hm, that could be a thing
m_w has joined ##openfpga
SuperChickeNES has quit [Ping timeout: 240 seconds]
ChickeNES has joined ##openfpga
<kc8apf>
That reminds me that I have friends I should visit on Bainbridge
noobineer has quit [Ping timeout: 240 seconds]
digshadow has joined ##openfpga
jhol has quit [Quit: Coyote finally caught me]
<azonenberg>
kc8apf: i'm on BI so come over any time
<kc8apf>
good to know
soylentyellow has quit [Ping timeout: 260 seconds]
<digshadow-c>
kc8apf: thats what I meant by "its a bit early"
<digshadow-c>
I actually have a real ROM that I had to do some more crazy bit manipulation on
<digshadow-c>
if that's a more interesting data point
<kc8apf>
the framing format is described in the datasheet
<digshadow-c>
right...
<kc8apf>
I'm getting back to experimenting with a library for writing bitstream assembler/disassemblers
<kc8apf>
xc2 might be interesting to start with
<azonenberg>
kc8apf: i'd love something nice for greenpak too
<azonenberg>
digshadow. mithro: rqou PAR'd the first working bitstream from hdl to jed for xc2c
jhol has joined ##openfpga
<azonenberg>
we had previously made working bitstreams by bit twiddling in a text editor but had no hdl support
<mithro>
azonenberg: Yeah
<mithro>
azonenberg: Been poking him to get that flow working for a while :-P
<mithro>
azonenberg: So happy to see it happening!
<azonenberg>
yeah i want to do more greenpak stuff too
<azonenberg>
right now its been halted for a long time b/c of higher priority obligations
<azonenberg>
So many things i want to do once i'm settled in at the new place and things have stabilized a bit...
<azonenberg>
kc8apf: So are you planning to swing by the island at some point? Did you have a time in mind?
<kc8apf>
probably not this weekend.
<azonenberg>
ah ok, when are you out here next?
<kc8apf>
May
<mithro>
azonenberg: I'm still wondering if it makes sense for vpr support for greenpaks?
<azonenberg>
oh thats not too far out
<azonenberg>
mithro: could it even work? its not a tile-based architecture
<kc8apf>
Pretty much 2x/month
<mithro>
azonenberg: Not sure
<azonenberg>
my whole goal of xbpar was to be a fundamentally different data model to target crossbar-based architectures vs tile based
<kc8apf>
April is an exception.
<azonenberg>
Then rqou had to go and do weird things in rust instead of just using c++ like a sane developer :p
<azonenberg>
i made xbpar a library for a reason
<mithro>
azonenberg: I don't see why you couldn't make it work - doesn't mean it would be any good :-P
<azonenberg>
mithro: lol
* whitequark
stares at "c++" and "sane" in the same sentence
m_w has quit [Ping timeout: 264 seconds]
m_w has joined ##openfpga
mumptai has joined ##openfpga
<awygle>
that ghdl thing is very interesting
<balrog>
yeah
<balrog>
but its dependence on GNAT/Ada, GCC, and GPLv3 license means fewer people will look at it
<balrog>
also the complexity of the parser (and the fact it's in Ada)
<azonenberg>
ada
<azonenberg>
... if VHDL was a normal software programming language
<azonenberg>
:p
<balrog>
azonenberg: Ada came first xD
<azonenberg>
i'm aware
<azonenberg>
but still
* awygle
is going to regret this question but...
<awygle>
what's wrong with GPLv3? other than that the existing tools are licensed differently
<awygle>
(of course no one knows ada, no argument there)
<rqou>
a lot of people don't _want_ anti-tivoization
<rqou>
and gplv3 is incompatible with gplv2
<awygle>
rqou: i never really had the impression that the issue was GPLv3 in particular, just a lot of people don't like GPL at all
<awygle>
i could be wrong of course
<whitequark>
some people (like me) are opposed to copyright in general
user10032 has joined ##openfpga
<awygle>
this is going to go off the rails rapidly, and while i'd love to have the conversation, i don't want to drag the whole channel with me, so consider my question withdranw
<rqou>
btw did you sit through the lecture of brian harvey explaining IP?
<awygle>
rqou: yes but i don't think i was listening
wpwrak has quit [Read error: Connection reset by peer]
wpwrak has joined ##openfpga
<rqou>
lol same here
<rqou>
but i listened for the IP discussion and only stopped paying attention in the therac-25 discussion :P
<rqou>
so yeah, this is the current state of ethics in computer science
<cr1901_modern>
therac-25 is fascinating. I don't see why you'd nod off there
<azonenberg>
yeah i cited it in my thesis and everything
<qu1j0t3>
there's a therac-25 every month now, it's a pity they teach that and everyone assumes "oh we do better now", but we don't. and that's what they should teach. Just that we don't really investigate or expose the constant trickle of deaths due to software today
<azonenberg>
qu1j0t3: [citation needed]
<qu1j0t3>
come on
<qu1j0t3>
do a back of the envelope
<azonenberg>
the only two major cases i know of are that and the toyota unintended acceleration suit
<qu1j0t3>
yes, but that's the PROBLEM
<azonenberg>
the latter is common knowledge in the safety engineering field
<azonenberg>
but, critically, never made it to court
<qu1j0t3>
software engineering has not substantively improved since Therac
<azonenberg>
and thus it's not legally proven that software killed them
<azonenberg>
because they settled
<qu1j0t3>
but the exposure to software and hrdware in terms of risk has gone up by orders of magnitude
<azonenberg>
I dont deny that
<azonenberg>
i just mean, i havent actually seen NTSB reports etc that actually implicate things
<azonenberg>
The two conclusions are that nobody's investigating or they're not happening
<azonenberg>
#1 seems more likely
<qu1j0t3>
so, even the most conservative back of the envelope says that thousands die every year due to software, but there is no will to examine this
<azonenberg>
But i have no data to support that
<qu1j0t3>
yes. nobody's investigating. we don't even have structures in place
<awygle>
NTSB is investigating the uber thing
<awygle>
apparently
<qu1j0t3>
ONE PERSON
<awygle>
qu1j0t3: i agree with you
<qu1j0t3>
that's probably THE highest profile death this year. Of course it will be investigated.
<qu1j0t3>
but none of the rest will
<awygle>
although honestly there will be many thousands of deaths from human-driven cars that have nothing to do with software that will go uninvestigated and unpunished
<awygle>
which is not an excuse
<awygle>
just perspective
<qu1j0t3>
i'm not even sure her death can be pinned on software engineering. it might be just that they turned off the car's native safety systems, apparently. or, deadly simply by design (i don't think anyone can claim the systems Uber is deploying aren't deadly)
<qu1j0t3>
look for a lot of lobbying against regulation of software safety lol
<azonenberg>
awygle: ok thats a bit of an exceptional case
<sorear>
i'm still inclined to view this as a hardware safety problem
<qu1j0t3>
anyway i think it's super unhelpful for curricula to focus on Therac, in short
<azonenberg>
qu1j0t3: meanwhile i'd back legislation mandating triple redundancy and formal verification in self-driving car systems
<azonenberg>
:p
<azonenberg>
qu1j0t3: its valuable specifically because it's a well studied case
<qu1j0t3>
azonenberg: So would I, but i think this is not enough :)
<azonenberg>
hypothesizing about other incidents without a full investigation is a lot harder to build a class around
<sorear>
a much smaller number of many-occupant vehicles operating on tracks separated from pedestrians would be far safer, but in the USA we take it for granted that single-occupant occupant-owned motor vehicles are the only way to transportation
<qu1j0t3>
azonenberg: the problems it creates (false conclusions, overshadowing much bigger problems today) may be much worse than any value it has as a case study
<qu1j0t3>
azonenberg: they could at least update to examples from this millennium
<qu1j0t3>
and then use Therac to show that nothing has improved
<azonenberg>
qu1j0t3: again, i dont think there have been well-investigated cases with proof software killed somebody
<qu1j0t3>
THAT would be a useful lesson
<azonenberg>
i'm sure people have died due to buggy software but nobody's done the legwork to prove it
<awygle>
i think the toyota thing is close enough for coursework
<qu1j0t3>
azonenberg: So you're saying this doesn't happen, in a world with like 200 billion embedded systems?
<qu1j0t3>
or is it not more likely that there's no framework within which to study it
<awygle>
qu1j0t3: that's not what he's saying. he's saying there isn't an obvious case study to use in a classroom setting.
<qu1j0t3>
eh ok sure, but that, again, is a symptom of a problem
<sorear>
safe cars ~ clean coal
<azonenberg>
qu1j0t3: There's no NTSB for non-transportation-related software-involved accidents
<qu1j0t3>
look at the computerisation of hospitals that has occurred SINCE Therac...
<qu1j0t3>
(hospitals alone)
<qu1j0t3>
azonenberg: Yeah. this bothers me :)
<azonenberg>
i bet a lot of incidents are just chalked up as "accidental death - equipment failure"
<azonenberg>
and nobody investigates further
<qu1j0t3>
yep
<qu1j0t3>
my gut says the same
<azonenberg>
But again, no case studies or court records to prove otherwise
<awygle>
sorear: except there are obvious widely deployed alternatives to coal
<qu1j0t3>
and probably a lot of lobbying to ensure this doesn't change
digshadow has quit [Ping timeout: 264 seconds]
<awygle>
... i should have just kept talking about licensing lol
<whitequark>
re: hospitals, it's not even that
<whitequark>
the additional workload placed on doctors by EHR systems (functioning as designed!) alone is killing a lot of people every year
<whitequark>
oh hang on
<whitequark>
now that you mention hospitals
<whitequark>
I have an excellent example for you, if I can dig out the article
<whitequark>
>According to a study published in December by the Pennsylvania Patient Safety Authority, the number of reports about medical errors associated with electronic records is growing. Of 3,099 incidents reported over an eight-year period, 1,142 were filed in 2011, more than double the number in 2010.
<whitequark>
Unlike U.S. medical-device makers, which must report all malfunctions, serious injuries and deaths involving their products to the FDA, software companies that make electronic medical records are under no such requirement.
<whitequark>
As a result, little is known about the risks of their systems, since there is no central database of error reports and makers of electronic records often prohibit customers from discussing unsafe processes. That practice creates “unacceptable risks to safety,” according to a 2011 report from the Institute of Medicine of the National Academies.
<Bike>
how did software engineering end up lacking all the controls other engineering has gotten over the years
<whitequark>
god damn it
<Bike>
also what the heck is the institute of medicine of the national academies.
<Bike>
sorry?
<whitequark>
I'm trying to find that article and instead I'm finding dozens of completely unrelated ones also about deaths caused by EHR
<whitequark>
by the way, one reason we don't know very much about these failures is because EHR vendors add gag clauses to contracts
<whitequark>
why is that shit even legal?
<Bike>
the prospect of an article like this being broken into chapters is pretty horrible on its own
<Bike>
because nobody made it illegal, i guess
<qu1j0t3>
> lobbying
<Bike>
probably couldn't legislate a general ban on gags in contracts
<whitequark>
tl;dr: a doctor needs to click like fifty times to prescribe something routine in Epic's system, the system spams you with bullshit alerts, and the interface is such that being slightly inattentive can result in the dose being 39 times higher than what it should be
<whitequark>
it did show an alert, which promptly got dismissed because it always shows nonsensical alerts
<whitequark>
and "No one at the center had ever heard of an accidental overdose this large—for Septra or any other antibiotic, for that matter—and nothing close had ever been reported in the medical literature."
<Bike>
oh, wait, when you put it like that i think i heard of this case before.
<Bike>
already horrified, no need for a repeat
<whitequark>
yeah, it's profoundly disturbing
<Bike>
i've been planning on going into biomedical engineering but things like this are urgh
<Bike>
that one cochlear implant thing is just stuck in my head now
<Bike>
not that that was software
<Ultrasauce>
just go work for elon musk's BCI venture in the secret lab doing human experimentation that probably will exist
<whitequark>
lol elon musk
<whitequark>
why does anyone take his BCI bullshit seriously
<Bike>
shudders
<Bike>
god when i was a kid i thought BCI was cool as hell. i still kind of think it''s cool as hell. but people like musk
<Bike>
so not cool
<Ultrasauce>
nothing wrong with being an anime supervillain
<Bike>
i don't have the hair
<Bike>
neither does musk
<whitequark>
oh please, anime supervillains have standards
<Bike>
i think the main thing i realized that was needing surgery for a consumer device is, actually, kind of bonkers
<whitequark>
awygle: btw got any plans for glasgow-jtag?
<whitequark>
I grabbed an ultraplus devboard and I think I'll look into implementing bitstream loading soon
<whitequark>
onto the FPGA via the Cypress chip
<daveshah>
whitequark: what devboard is this? don't know of any ultraplus board with a Cypress chip...
<whitequark>
daveshah: it's a board I'm designing
<daveshah>
whitequark: Awesome
<whitequark>
daveshah: it can be described like "bus pirate but with an FPGA"
<daveshah>
oh nice
<whitequark>
the default mode is emulating an FT232 with its MPSSE and being a JTAG cable
<whitequark>
digilent clone
<whitequark>
but you can e.g. reconfigure it to act like eight serial ports
<whitequark>
or two JTAGs and two serial ports
<whitequark>
or a JTAG and an SWD or SPI and I2C or whatever
<rqou>
whitequark: i just read your link about the UCSF overdose
<rqou>
all i can say is "wow, holy shit"
<rqou>
i know i like to poke fun at infosec and "security toasters" but this is much worse
<azonenberg>
whitequark: aviation systems are far from perfect but i think they're the best we've got now
<azonenberg>
both in terms of UI security and sane architecture
<azonenberg>
automotive, medical, and scada are probably 20 years behind
user10032 has quit [Quit: Leaving]
<awygle>
whitequark: planning to do the loopback and the clock divider commands this weekend
<awygle>
tbh depending on your goal, if the target is "get a working prototype ASAP" we'd be better off with me on PCB design, i still don't know Migen worth a damn
<awygle>
but i'm enjoying learning so i'm happy with the current arrangment too, whatever you wanna do
<rqou>
awygle why are you working on this and not PAR? :P
<awygle>
rqou: why are you working on xc2c and not homecmos?
<awygle>
na i just had plans in this direction and saw a chance to hop on board with whitequark
<rqou>
homecmos isn't happening until at least after I graduate
<awygle>
i do want to spend some time prototyping the PAR engine, basically ignoring the ecosystem issues. i'm planning to take close to a week off work when my current project is finished, probably do some then.
<azonenberg>
rqou: yeah i want to get back to it post move
<azonenberg>
that kinda has always been the endgame of my home lab efforts
<pie_>
rqou, shouldnt you put that in the commit message then or something
<rqou>
i kinda did
<rqou>
but yeah, i didn't write the root cause
<pie_>
maybe you should?
<rqou>
too late :P
<pie_>
find a solution (tm)
<pie_>
:P
<awygle>
rqou: does your "Swap it back" function not actually swap?
<rqou>
correct
<awygle>
(not a function. block.)
<rqou>
it doesn't swap the "loc" field correctly
<awygle>
(that also means somehthing in rust. whatever that thing is.)
<rqou>
anyways, did you know that copypasta is bad? :P
<awygle>
apparently you didn't even copy it :p
<rqou>
that too
<rqou>
an actual copypasta would have been correct
<awygle>
realistically, you copied it and then modified _one_ copy
<awygle>
which is in fact why copypasta is bad
<awygle>
(well, one reason)
<rqou>
and as you can see, the copies have now been deleted
<awygle>
but i just burned six hours on a printline so... glass houses
<awygle>
i admit i don't fully understand why that had to be a macro
<awygle>
instead of just a function
<rqou>
declaring a function at that location will end up mutably borrowing macrocell_placement
<rqou>
ok, i guess it could have been a function if you passed in macrocell_placement as an argument
<rqou>
rather than having it automatically captured
<awygle>
right
<awygle>
okay so my understanding was right
* awygle
awards himself one point
* awygle
is now at minus several thousand for the day
Zorix has quit [Quit: Leaving]
Zorix has joined ##openfpga
<whitequark>
awygle: it's not super urgent, i feel like it would be better if you picked up some migen skills and i, conversely, picked up some kicad skills
<rqou>
wait, you _don't_ use kicad?
<whitequark>
of course i'll be glad to see you helping with the pcb
<whitequark>
rqou: i didn't until recently
<whitequark>
i started using it uh, about two months ago
<rqou>
what did you use before?
<whitequark>
eagle duh
<awygle>
whitequark: copy. let me know if a timeline suddenly manifests itself.
<rqou>
lol ok
<whitequark>
but they pissed me off with their new subscription model
<whitequark>
and also I looked at kicad's libraries and liked them more
<whitequark>
and then digikey decided to provide kicad libraries
<whitequark>
and that made me jump ship at last
<awygle>
that subscription thing really pissed a lot of people off lol
<awygle>
i'm not sure what happened _exactly_ but i somehow was given a lifetime subscription to circuitstudio
<awygle>
i think it might be because i paid ~$3k for it and then they dropped the price to ~$500
<awygle>
o hey speak of the pcb design! my new mouse was just delivered, that will make things easier lol
noobineer has joined ##openfpga
<digshadow>
mithro: Verilog first appeared in 1984 while the XC2064 was announced in 1985
<digshadow>
to add more depth to the earlier verilog question
<digshadow>
so even closer than I thought
noobineer has quit [Ping timeout: 276 seconds]
<rqou>
ugh, i hate leakage inductance
<rqou>
so unintuitive (at least to me)
<awygle>
rqou: just graduate already :p
<rqou>
lol f*ck you
<rqou>
random troll question: when is pie_ going to graduate? iirc he's the other person here who's been a student forever
<pie_>
haha
<pie_>
well, bsc fin next year hopefully
<azonenberg>
Better than bsc RST i guess
* rqou
slaps azonenberg
<pie_>
heh
<awygle>
rqou: what level of fancy paper are you currently chasing?
<rqou>
it's called a master of engineering program
<rqou>
so it's basically a coursework (vs research) masters + business/soft-skills stuff
<awygle>
ah yeah k
<awygle>
i just couldn't remember if it was M or D
<pie_>
does he want the D
<rqou>
no, only azonenberg does :P
<pie_>
he has the D though no?
<pie_>
i though the did
<pie_>
*thought he did
<azonenberg>
lol
eric_ has quit [Read error: Connection reset by peer]