02:09 <rqou> O_o electroboom is now doing "serious" educational videos that don't just involve shocking himself: https://www.youtube.com/watch?v=vn4J8RcMGrM

02:10 <awygle> That seems like dangerous cross promotion lol

02:10 <rqou> dangerous?

02:11 <awygle> "hi I'm teaching you things" "oh cool I'll go to his other videos to learn more things"

02:11 <awygle> "Oh whoops I'm dead now"

02:56 <tinyfpga> mintro: been reading up on 7-series multiboot. Looks like I need to instantiate an internal configuration primitive and send a command that tells it to reconfigure from a specific address in SPI flash

02:57 <tinyfpga> mithro: once I have that it should be very similar to how the bootloader works on ice40

03:59 <mithro> tinyfpga: yeah

07:20 <whitequark> awygle: pong

07:21 <whitequark> what up? i was sleeping

09:30 <ZipCPU|Laptop> tinyfpga: I've got multiboot working as a wishbone peripheral if you are interested.

09:31 <ZipCPU|Laptop> See https://github.com/ZipCPU/wbicapetwo Designed to work with 7-series devices, includes (untested) code for Spartan 6's as well.

15:18 <tinyfpga> ZipCPU: nice, I’ll take a look. Probably won’t use the whole wishbone peripheral, but it will be great to use as a reference

15:20 <tinyfpga> ZipCPU: I’m going to create a module with a synchronous boot signal that will drive the ipace2 module with commands from a small ROM

15:51 <tinyfpga> ZipCPU: or...after taking a closer look, I might use the wishbone peripheral

17:03 <awygle> whitequark: so was i

17:04 <awygle> whitequark: i'm trying to implement the loopback mpsse commands by reassigning tdo in the MPSSEBus module but i am failing to update my loopback mux select signal from the command processor for reasons i don't understand

17:05 <awygle> if you have a second, can you take a look at https://github.com/awygle/Glasgow-JTAG/tree/loopback ? i'm sure i am making a simple migen error

17:08 <whitequark> awygle: if you do .eq() in an FSM action you get a combinatorial assign

17:08 <whitequark> if you do NextValue you get a register

17:10 <awygle> whitequark: ah ok, now the value is changing. thanks

22:39 <rqou> somewhat unclear, but code protection bypass on psoc1: https://syscall.eu/blog/2018/03/12/aigo_part2/

22:39 <rqou> cc azonenberg, cyrozap, pointfree

22:44 <pointfree> rqou: Wow interesting

22:52 <pointfree> rqou: The PSoC 5LP SPC core is an M8B, an older version of the M8C (M8C == PSoC 1).

23:02 <pointfree> rqou: This could make hack upgrades to the PSoC 5LP more likely is all I'm going to say.

23:02 <rqou> wait how? what's SPC?

23:03 <rqou> does the psoc5 boot off of a potato that has to then boot up the arm core?

23:12 <pointfree> rqou: It's the "System Performance Controller" it's used for the rw interface/access to non-volatile memory etc.

23:40 <rqou> it seems like in general we need more RE on debugger protocols

23:40 <rqou> tons of overlooked bugs there

23:51 <pie_> so they used an older version for the newer one?

23:52 <rqou> i assume it's a nice tiny potato-quality core good for running a single state machine

23:54 <kc8apf> After 7h thrown at Make, TCL, and more, I have a build environment that can clean up after Vivado.

23:54 <kc8apf> now, back to working out Apple][ MMU details