<awygle>
also PSA the SystemVerilog 2017 standard is available free through IEEE GET currently
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<balrog>
awygle: isn't that what sci-hub is for? :D
<awygle>
balrog: well yes, but some people don't like to do that (and on the off chance they track such things it'd be nice to show that people like the GET program, by way of encouragment)
<rqou>
or just join me on the 136.152.0.0/16 network :P
<rqou>
awygle: come visit? :P
<awygle>
rqou: don't they have some kind of alumni vpn?
<rqou>
i don't know
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<rqou>
the CAA membership library access does _not_ include vpn
<awygle>
bummer
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<rqou>
apparently it has to do with the university's licensing agreements
<rqou>
<insert "we really need open access" thing here>
<awygle>
lying about your source IP address seems like the kind of thing that probably isn't hard to do
<awygle>
although i guess the returning packets wouldn't go to you
<azonenberg>
awygle: the hard part isgetting the reply
<azonenberg>
yeah
<awygle>
that was dumb
<awygle>
i assume people do this kind of shit for DoS purposes? like that thing with bouncing e-mails, or ordering a pizza to somebody else's house?
<azonenberg>
isps are getting better at blocking it
<azonenberg>
i.e. drop outbound packets not from the right subnet
<awygle>
unrelated, someone please order a pizza to my house
* awygle
is hungry
<azonenberg>
awygle: none pizza with left beef, right?
<awygle>
azonenberg: i acknowledge your reference but shudder at the thought of receiving such a travesty
<azonenberg>
lol
<rqou>
azonenberg how is your house?
<rqou>
"are we there yet?" :P
<azonenberg>
rqou: All bedrooms are substantially done with power wiring
<azonenberg>
Still have to hook up several strings of outlets to each other through the living room ceiling (not yet removed)
<azonenberg>
wire two walls of the garage
<azonenberg>
frame and wire the office
<azonenberg>
wire the dining room
<azonenberg>
Connect the first and second floor smoke detector circuits
<azonenberg>
Run data conduit to 1.5 (one is partially wired) upstairs bedrooms, the living room, and dining room
<azonenberg>
oh and install a closet light or two
<azonenberg>
Then i have to run the last ~40 feet of cable tray
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<awygle>
azonenberg: are you, physically, with a hammer, framing e.g. the office?
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<azonenberg>
awygle: yes
<azonenberg>
The existing framing was atrocious and had to be completely removed in that room
<azonenberg>
they had untreated 2x4s flat-wise in direct contact with concrete
<azonenberg>
no vapor barrier
<awygle>
well yes, that's obviously terrible
<azonenberg>
about 1" of foam insulation jammed between them, that's like $-6 or something
<azonenberg>
R-6*
<awygle>
i would just pay somebody to do that lol
<azonenberg>
So now i'm putting down continuous foam over the concrete as a vapor barrier plus extra insulation and waterproofing
<awygle>
not that i can't do it/haven't done it before
<azonenberg>
then new 2x4 framing, then fiberglass insulation in that
<awygle>
bleh fiberglass. so glad my life hasn't brought me in contact with it recently.
<azonenberg>
you did see what i wear when working with it in the attic right?
<azonenberg>
the old stuff is blow-in fiberglass plus sawdust insulation
<azonenberg>
its a nightmare
<azonenberg>
I wear a full body tyvek suit with booties and hood
<azonenberg>
a full-face respirator
<azonenberg>
and heavy neoprene gloves taped at the wrists
<azonenberg>
it's pretty much a level c hazmat suit
<azonenberg>
no glass splinters have got through THAT yet
<rqou>
azonenberg: not planning on using any el-cheapo urethane foam insulation that offgases amines? :P
<azonenberg>
lool no
<azonenberg>
i'm using foil faced XPS
<azonenberg>
aaand putting in fall protection anchors in the attic before i do demolition over the stairwell
<azonenberg>
i'm not super concerned about the regular attic spaces but a 14-foot drop with precarious footing is a bit much
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<rqou>
hmm apparently they offgas isocyanates, not amines
<rqou>
totally better, right? :P
<azonenberg>
rqou: i havent smelled anything yet, polystyrene is generally pretty stable
<azonenberg>
I'm sure whatever comes off the newly installed paint (and the glue i hung the foam with) will be a lot worse
<rqou>
yes, it's polyurethane that tends to be a problem
<rqou>
from what I've heard it's often because of improperly trained techs who don't set up the equipment properly to mix the components properly
<azonenberg>
this is factory made foam boards cut to size
<azonenberg>
so it's already cured
<rqou>
yeah, definitely no problem there
<rqou>
oh, i think the messages got a bit mixed up
<rqou>
i was still referring to el-cheapo spray foam, not the stuff you are using
<rqou>
no "budget" home renovations for you? :P
<azonenberg>
The only thing i use spray foam for is sealing gaps and holes
<azonenberg>
not bulk cavity insulation
<azonenberg>
i want something i can remove to do repairs :p
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<awygle>
the ice40 BGAs are really really small. i didn't realize they're mostly 0.4mm space.
<awygle>
for the LP series
<azonenberg>
lol
<azonenberg>
You see why i'm mostly a xilinx guy?
<azonenberg>
Nice roomy 1mm pitch
<balrog>
azonenberg: you're not making small devices :P
<azonenberg>
lol
<azonenberg>
yeah most of my planned gizmos are 1U form factor lol
<azonenberg>
or fairly large blades
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<awygle>
i really want to do something with the 0.4mm 81-ball package but the board would be $$
<awygle>
what's that like 3mil trace/space?
<azonenberg>
i'd do probably 0.125mm (5 mil) trace/space for fanout
<azonenberg>
then microvias under the array for the inner balls
<azonenberg>
:p
<awygle>
hmm yeah VIP or microvia is probably more doable than crazy trace/space
<awygle>
not that those things are cheap lol
<awygle>
tinyfpga: you used the 81-ball 0.4mm package on the B2 right?
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<rqou>
azonenberg: how legit is the black mesa labs "big hole to solder qfn pad from the opposite side" trick?
<rqou>
does that actually give acceptable impedance/thermal conductivity?
<rqou>
is it? i always got the impression it was a "hobbyist" hack
<awygle>
and i don't see why it wouldn't give fine performance
<rqou>
it just feels like a hack
<awygle>
qfn is a hack :P
<azonenberg>
rqou: bml doesnt use kicad or any sane eda tool
<azonenberg>
he doesnt even ERC
<azonenberg>
i'm impressed he pulls off as much as he does
<rqou>
yeah? i usually don't ERC either :P
<rqou>
i use "highlighter ERC"
<awygle>
i see that "yolo i'm hardcore" attitude a lot and i don't really understand it. i usually go through a full DFM with my manufacturer if i'm doing a "real" board
<rqou>
er, it's not because i'm being "hardcore"
<rqou>
it's just that most ERC kinda sucks and isn't that useful
<azonenberg>
o_O
<azonenberg>
if anything i want a better erc
<awygle>
rqou: not intended as a dig at you specifically, although my experience does not match yours
<azonenberg>
i want vih/vil/voh/vol on every gpio
<azonenberg>
specified and checked as part of the erc
<awygle>
(maybe kicad's erc is terrible, i still haven't done any kicad designs)
<azonenberg>
i want smps modules that include the vout refernece calculation internally
<rqou>
yeah, i've more or less only used "net class matching"-type ERCs
<rqou>
which aren't really smart enough
<azonenberg>
and will calculate the output voltage
<rqou>
EAGLE and afaik kicad are both like this
<azonenberg>
and check against the legal vdd range of each device
<awygle>
i will settle for "intelligently calculates impedance and yells at me if my GCPW geometry goes crazy for a few inches"
<azonenberg>
that's more of a layout drc thing
<awygle>
true
<rqou>
i do use layout drc of course
<azonenberg>
also knowing that the erc/drc is insufficient
<azonenberg>
i use my own checklist on top of it
<rqou>
i just don't use the classic "net class" ERC that loves to say "hurr durr, strap pins (marked IO) are not compatible with VCC (marked as power supply)"
<awygle>
yeah it's a pipeline. ERC/DRC->checklist->DFM review
<awygle>
rqou: mark your strap pins as I.
<rqou>
but that's not what they are
<azonenberg>
awygle, rqou: see, there's an obvious solution
<azonenberg>
use 0-ohm resistors to strap
<rqou>
lol fine :P
<awygle>
if you're attaching a pin directly to VCC/GND, it had better be an I
<azonenberg>
This bypasses the ERC issue AND makes rework a lot easier
<awygle>
i usually strap with 10k
<azonenberg>
it depends on the signal
<awygle>
unless the datasheet says otherwise
<azonenberg>
dedicated straps that cannot be output are tied with 0
<azonenberg>
if it's a bidir pin i use 10k unless i see a need to go otherwise
<azonenberg>
to prevent frying things
<azonenberg>
(that said, i have a general policy of avoiding strap pins as io unless i am forced to)
<awygle>
i use 10k on dedicated straps because i have more 10ks than 0s at home :P
<azonenberg>
lol i see
<rqou>
also, how 0 is your 0? :P
<azonenberg>
i have full reels of each iirc
<awygle>
10k is my "standard resistor"
<rqou>
apparently that can actually be a problem
<azonenberg>
rqou: if it mattered i'd characterize
<azonenberg>
most of the time i dont care
<awygle>
like often on power supplies i'll say "okay top is 10k, what does that make bottom"
<rqou>
i remember a blog post where some people have managed to f*ck this up
<awygle>
or vice versa
<rqou>
but they were using 0ohm straps on a PSU, so...
<rqou>
:P
<awygle>
i've had an out-of-spec 47k resistor before
<awygle>
it came in at like 50k and set a current limit low enough that it tripped
<awygle>
(which was good because the board was drawing 3x the power we expected and we'd never have caught it without that)
<azonenberg>
lool
<azonenberg>
awygle: if i actually care, like for a psu
<azonenberg>
i normally use 1% or even 0.x% tolerance
<azonenberg>
if one of those came in out of spec i'd be pretty surprised
<awygle>
azonenberg: this was a 1%
<awygle>
i used to use 0.5 or 0.1 for analog stuff, but then i a) looked at my BOM cost and b) did the math on the tolerance swing and decided it was fine :P
<awygle>
my schematic checklist includes a table next to every PSU saying the designed output voltage and both extremes of output voltage given (input tolerance + resistor tolerance)
<azonenberg>
i should start doing that
<rqou>
we really need more scriptability in EDA tools
<azonenberg>
right now i've mostly gone with <= 1% tolerance and called it good
<rqou>
hence why i quite liked the proprietary PLECS we use for class
<rqou>
because it's fully XMLRPC-controllable
<azonenberg>
rqou: yes, IMO a schematic symbol should be an active component
<azonenberg>
that can integrate with drc/erc etc
<azonenberg>
and complain about things like a missing strap
<rqou>
afaict kicad's current mechanism is just some shitty SWIG thing
<azonenberg>
or power supplies fed by the wrong voltage
<rqou>
that barely works
<azonenberg>
awygle: in general my bom cost is dominated by FPGAs
<rqou>
it seems like it's easier to manually parse a kicad schematic/board, do the needed change, and write the result back out than to try to use the internal scripting API
<azonenberg>
and pcb manufacturing cost
<azonenberg>
coming in at a distant third are large ceramic caps
<rqou>
O_o
<rqou>
what
<awygle>
rqou: yes, it's SWIG, and it only works in layout iirc
<azonenberg>
rqou: have you not seen the caps i use in my designs?
<rqou>
no?
<azonenberg>
iirc on my first 7-series PCB
<azonenberg>
i had a 330 uF 1812 mlcc
<azonenberg>
that was like a $6 cap
<rqou>
wtf why
<azonenberg>
on vccint
<azonenberg>
The ESR etc blew tantalums out of the water
<rqou>
that's insane for the given form factor
<azonenberg>
this was on the 1v0 rail
<azonenberg>
i think the cap had a 4V rating?
<rqou>
hmm, i thought too low ESR can cause the SMPS control loop to go unstable?
<azonenberg>
I generally pick smpses that are designed to handle this
<azonenberg>
it's older LDOs that had bigger problems with this iirc
<rqou>
ah ok
<rqou>
but but azonenberg, if you don't use tantalum caps, how else can you go and exploit poor children in the congo? :P :P :P
<qu1j0t3>
:(
<qu1j0t3>
#tooReal
<rqou>
you'll need to go buy a blood diamond instead :P :P :P
<azonenberg>
I take that back
<azonenberg>
it was more like a $4 cap
<azonenberg>
and it was 1210
<azonenberg>
587-3976-1-ND
<rqou>
that's still insane capacitance for the form factor
<azonenberg>
Yes
<azonenberg>
I do 100% ceramic on all of my low voltage rails
<awygle>
did you need that much cap/that little ESR?
<awygle>
just afraid of splosion?
<azonenberg>
awygle: for vccint? it was a bulk cap and a tantalum probably would have been fine, but i generally avoid using them
<azonenberg>
wet electrolytics tend to fail too
<awygle>
yeah wets are bad
<azonenberg>
if i use electrolytics at all they're solid polymer dielectric
<azonenberg>
the high end nichicons or something
<awygle>
weve had this convo before i think
<azonenberg>
Probably
<azonenberg>
The way i see it, if i'm spending a month or two of my time
<azonenberg>
and several thousand dollars on pcb+components
<azonenberg>
i am not going to cheap out on the passives
<awygle>
the last thing i built that needed 330 uF was a coilgun lol
<azonenberg>
This was what xilinx recommended as the vccint bulk cap on a 7k70t iirc
<rqou>
have you considered something physically bigger? :P
<azonenberg>
rqou: if you look for 330uf mlcc thats about the option you get
<azonenberg>
there's 2-3 competing parts from other vendors with substnatially identical specs
<azonenberg>
awygle: i dont even want to think about what some of the big virtexes need
<azonenberg>
we're talking maybe a 40 amp rail at 800 mV
<awygle>
i wonder what level of cap change you get from 1V on something like that
<azonenberg>
+/- 5 mV or some crazy tight spec
<azonenberg>
awygle: -10%
<azonenberg>
i checked the curve
<awygle>
usually if cap/size is too high you get crazy sag
<rqou>
no +80/-20 for you? :P
<azonenberg>
Without exception, i use caps that have curves easily available
<azonenberg>
If i have curves linked on the digikey page you pretty much guarantee a design win if the part is any good
<awygle>
i do too, and i derate voltage by 50% (which doesn't actually help for small X7Rs)
<rqou>
oh wtf there really aren't any physically larger 330uf ceramic caps
<rqou>
all the larger ones are tantalum
<azonenberg>
awygle: i dont do derating beyond looking at the curves
<azonenberg>
Samsung gets most of my design wins for caps b/c i love their datasheets
<azonenberg>
awygle: that said, in order to get a good point on the curve i normally end up using the part at like 1/3 of the rated max if not less :p
<pie_>
time to write an electronics compiler <rqou> we really need more scriptability in EDA tools
<rqou>
pie_ where have you been?
<awygle>
pie_: pcbhdl
<rqou>
^ this
<pie_>
vaguely around
<pie_>
i was actually alluding to that :P
<awygle>
you can get a 4V 330 uF Al poly cap for $1.46, which isn't too bad
<awygle>
ESR 15 mOhm
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<awygle>
big though
<rqou>
oh btw on a different topic: lab for power electronics today was "tear down an RE a power supply from this box"
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<rqou>
apparently i decided to be a genius and purposely picked one of the hardest ones
<pie_>
my electrodynmics teacher just covered phasors ...so much better than the way we learned it in some second semester intro electronics class, ugh
<awygle>
that sounds pretty fun
<pie_>
rqou, we'd be ashamed of you otherwise :P
<ZipCPU>
Anything like star trek? That would be a lot of fun.
<rqou>
a 90W laptop charger of some kind with EMI filtering, active PFC, and afaict adjustable voltage
* awygle
still doesn't understand phasors
<qu1j0t3>
So you left... stunned? pie_
<ZipCPU>
Did anyone get hurt?
<ZipCPU>
:P
<pie_>
qu1j0t3, not really because id gone and barely learned it during htat class, but it was just sooooo much better
<awygle>
i think phasors are one of those "let's explain it in an easy way!" thing that made no sense to me and then when i got to the "hard way" i was pissed they hadn't taught it all along because it made way more sense
<pie_>
*barely learned it for the test in the 2nd semester class
<pie_>
^for lulz
<awygle>
(see also Root Locus plots)
<qu1j0t3>
awygle: Like M*****
<azonenberg>
awygle: oh so the other thing
<azonenberg>
the reason that i love ceramic
<azonenberg>
is they're nice and flat
<pie_>
to be fair i think we involved maxwells equatins somehow this time but im not 100% sure offhand
<azonenberg>
Which is important if you're making hardware that may eventually live in a blade chassis with ~20mm pitch to the next blade
<azonenberg>
including pcb thickness and components on both sides
<rqou>
btw azonenberg what do you think about those "axis flipped" ceramics that have the terminals on the long axis?
<awygle>
azonenberg: the al poly i referenced was also flat, i hate the can ones (mostly on aesthetic grounds tbh)
<awygle>
rqou: good inductance performance
<awygle>
see also X2Y caps
<pie_>
awygle, complex analysis is underrated
<pie_>
^not that id have the experience to back that p