soylentyellow has quit [Ping timeout: 246 seconds]
m_t has quit [Remote host closed the connection]
eric_j has quit [Read error: Connection reset by peer]
eric_j has joined ##openfpga
digshadow has quit [Ping timeout: 264 seconds]
seu has quit [Ping timeout: 240 seconds]
Dolu has joined ##openfpga
Dolu2 has quit [Ping timeout: 246 seconds]
digshadow has joined ##openfpga
pie_ has joined ##openfpga
soylentyellow has joined ##openfpga
egg|egg has quit [Read error: Connection reset by peer]
unixb0y has quit [Ping timeout: 268 seconds]
unixb0y has joined ##openfpga
<fouric> qu1j0t3: I know of a few, but I've always been wary of "transpiled" languages, and Verilog seems like an especially janky target.
Dolu has quit [Read error: Connection reset by peer]
<qu1j0t3> yeah, i don't come from that position. Compilers underpin everything we do. They work.
<qu1j0t3> they let us work at appropriate levels of abstraction
<qu1j0t3> and also we can't be stuck with verilog forever, just as we're not stuck with assembly.
<fouric> Well, I guess I'll give it a shot.
<fouric> Erm, "one of them"
<qu1j0t3> yeah, that's the best approach i think
<qu1j0t3> try em out
<fouric> Chisel looks interesting, maybe I'll find someone who can show me how to actually get Verilog out of it.
<qu1j0t3> i've played with it briefly
<qu1j0t3> the SpinalHDL guy has a strong critique of CHisel, lol
<qu1j0t3> but Chisel has hosted some pretty large CPU designs
<awygle> I've asked this before but is Chisel FIRRTL?
<awygle> My resistance to NuHDL languages is that we still don't have good support for SystemVerilog or VHDL. It feels like we haven't yet implemented ANSI C but we're trying to jump to Nim.
GenTooMan has quit [Quit: Leaving]
Bike has quit [Quit: Lost terminal]
<rqou> awygle: want to help? :P
<rqou> help me implement VHDL
<awygle> rqou: I know zero VHDL though
<awygle> Also you used bison which I hate
<awygle> If it's all the same to you I'd prefer to keep complaining impotently :-P
<lain> I'll probably never finish it, at least not in its current form, but when I was working on hdl# I just had my "compiler" spit out VHDL, and allowed you to define external interfaces for interop
<lain> I mean
<lain> it's a hack, but it's an easy to implement hack
<lain> :P
<rqou> awygle: port the parser to a different framework?
<rqou> the rules were intended to not use too many bison extensions
<qu1j0t3> fouric: yeah
<rqou> although it is currently a bit busted and LR(k > 1)
<rqou> it's very "cs164" including manually handling associativity and precedence
rohitksingh_work has joined ##openfpga
digshadow has quit [Ping timeout: 276 seconds]
<azonenberg> qu1j0t3: i see verilog as more like the C of hdl
<azonenberg> assembly would be more like XDL :p
<azonenberg> i.e. a human readable 1:1 mapping of the binary
<qu1j0t3> my metaphor wasn't supposed to be taken so literally
<qu1j0t3> i agree that Verilog ~~ C is a good metaphor
<awygle> AIGER is asm
<awygle> Or blif maybe
<azonenberg> no, that doesnt have placement info
<azonenberg> that's more like an IR
<azonenberg> tech dependent, sure, but not 1:1 with the bitstream
rohitksingh_wor1 has joined ##openfpga
rohitksingh_work has quit [Ping timeout: 276 seconds]
soylentyellow has quit [Ping timeout: 256 seconds]
digshadow has joined ##openfpga
user10032 has joined ##openfpga
pakesson has quit [Ping timeout: 265 seconds]
pakesson has joined ##openfpga
oeuf has joined ##openfpga
cr1901_modern has quit [Read error: Connection reset by peer]
soylentyellow has joined ##openfpga
user10032 has quit [Remote host closed the connection]
uovo has joined ##openfpga
_whitelogger_ has joined ##openfpga
sgstair has quit [Ping timeout: 264 seconds]
indy_ has joined ##openfpga
Bike has joined ##openfpga
indy_ is now known as indy
sgstair has joined ##openfpga
seu has joined ##openfpga
rohitksingh_work has joined ##openfpga
rohitksingh_wor1 has quit [Ping timeout: 256 seconds]
Bike is now known as Bicyclidine
sgstair has quit [Ping timeout: 240 seconds]
rohitksingh_wor1 has joined ##openfpga
rohitksingh_work has quit [Ping timeout: 256 seconds]
rohitksingh_wor1 has quit [Read error: Connection reset by peer]
m_t has joined ##openfpga
genii has joined ##openfpga
soylentyellow has quit [Ping timeout: 276 seconds]
rohitksingh has joined ##openfpga
eduardo__ has joined ##openfpga
eduardo_ has quit [Ping timeout: 264 seconds]
Xark_ is now known as Xark
Xark has quit [Changing host]
Xark has joined ##openfpga
digshadow has quit [Quit: Leaving.]
digshadow has joined ##openfpga
Zorix has quit [Ping timeout: 252 seconds]
Zorix has joined ##openfpga
Ultrasauce has quit [Remote host closed the connection]
rohitksingh has quit [Ping timeout: 240 seconds]
<rqou> wow, sf.net git is slow as shit
<rqou> why do people still use it?
<qu1j0t3> that is definitely unclear.
<rqou> although apparently a non-asshole bought them a while back and is trying to clean up their tarnished reputation
sgstair has joined ##openfpga
cr1901_modern has joined ##openfpga
Ultrasauce has joined ##openfpga
Ultrasauce has quit [Read error: Connection reset by peer]
Ultrasauce has joined ##openfpga
<lain> did you see that sourceforge was down for like two weeks recently?
<lain> and not just like "brb maintenance" down, they were moving datacenters and managed to just throw up php and database errors for two weeks straight
<lain> it was amazing
<lain> anyone still using sf after that ... I just don't know :P
<Ultrasauce> where else are they gonna get their malware fix
mumptai has joined ##openfpga
<kc8apf> awygle: FIRRTL is a specification derived from Chisel syntax. The first few sections of the FIRRTL PDF talk about how it came to be because Chisel has no formal spec and relied on being implemented in Scala
<kc8apf> I'm all for building higher-level HDLs. I agree some lower-level languages that focus solely on synthesizable constructs and mapping to bitstreams is important.
<qu1j0t3> lain: o_O
sgstair has quit [Ping timeout: 240 seconds]
<qu1j0t3> lain: I guess it was one of those rapid unscheduled redeployment things?
<qu1j0t3> lain: i had to help a client with one of those over new year's 2017.
<qu1j0t3> Old developers: "We're pulling the plug on your complex undocumented marketing and reseller portal on Dec. 30."
<qu1j0t3> "here's an out of date backup"
<lain> lol
<lain> yaaay :|
<lain> "In the past two weeks there have been three significant outages of SourceForge's download services. The first was due to a datacenter move. The second, earlier in the week, was due to distributed denial of service attack (DDoS). This current multi-day outage which appears to have begun on Feb 28 is due to an unknown cause. There is currently no ETA or explanation. No details have been posted to the
<lain> SFNet_ops Twitter feed and a full day will go by without updates."
<lain> dunno who portableapps.com is but this is an indication of the length and severity of the outage
<awygle> wow, "due to an unknown cause" is not what you want to hear lol
<lain> aye
digshadow has quit [Quit: Leaving.]
digshadow has joined ##openfpga
<qu1j0t3> indeed
<qu1j0t3> seems to be the new team eh
<mithro> Afternoon!
<mithro> hey kc8apf, you should be recovering watching TV or something, not reading about HDLs :-P
<kc8apf> I'm doing both _and_ taxes
<kc8apf> I can kinda think for brief moments.
<qu1j0t3> ugh don't remind me it's tax time :<<
sgstair has joined ##openfpga
<rqou> whee, funemployed means no taxes
<rqou> (but also no money)
<awygle> it turns out if you spend a year hemmoraging money you save a lot on taxes the next year
<rqou> do you?
<rqou> anyone got a bug like that?
<rqou> azonenberg?
fouric1 has quit [Quit: WeeChat 1.9.1]
fouric has joined ##openfpga
pie_ has quit [Remote host closed the connection]
pie_ has joined ##openfpga
GenTooMan has joined ##openfpga
genii has quit [Quit: GO LEAFS GO !!]
mumptai has quit [Quit: Verlassend]
Bicyclidine is now known as Bike
seu has quit [Remote host closed the connection]
<rqou> so protip: if debugging x-using applications, use Xvfb
seu has joined ##openfpga
finsternis has quit [Quit: Lost terminal]
finsternis has joined ##openfpga