<digshadow>
azonenberg: meeting lekernel for dinner tomorrow
<digshadow>
has he been involved with openfpga stuff at all?
<rqou>
wait, what is the context for this?
<rqou>
can i somehow join in?
<rqou>
(also, idk if azonenberg is back from vacation yet)
Patater has quit [Ping timeout: 240 seconds]
digshadow has quit [Ping timeout: 276 seconds]
Patater has joined ##openfpga
theMagnumOrange has quit [Ping timeout: 240 seconds]
awygle has joined ##openfpga
theMagnumOrange has joined ##openfpga
enriq has quit [Quit: My MacBook has gone to sleep. ZZZzzz…]
enriq has joined ##openfpga
<awygle>
is BLIF like... isometric to RTLIL?
<awygle>
is there a bijection between the two?
<rqou>
i don't think so?
<rqou>
afaik BLIF can represent arbitrary netlists, whereas RTLIL only has a very specific set of cells
<awygle>
hm. gotta read more.
<rqou>
afaik RTLIL isn't a file format at all
<rqou>
it's just an in-memory representation
<awygle>
it's amazing to me how different people's styles of writing C++ can be
<rqou>
yeah, clifford's and azonenberg's feel totally different
<awygle>
neither clifford's nor cseed's are much like mine. i've only lightly worked with azonenberg's but it seems a closer dialect
<rqou>
this is the problem with using only the "good subset" of C++ is that everybody's subset is different
<awygle>
even when you get past functional differences you have "using namespace", macros like YOSYS_NAMESPACE_BEGIN, brace styles... all this little stuff that i _know_ what it's saying but it takes a brain cycle to do the translation every time
<rqou>
what are you doing with yosys?
<awygle>
thinking about inputs to and working data structures for a placement tool
<rqou>
shouldn't you be looking at VPR/arachne?
<rqou>
(i've never looked into either)
<awygle>
arachne eats BLIF, and while i agree with most of its data structures i don't like their implementations in most cases
<awygle>
lots of parallel containers with indexes to go between them... it's kind of hard to explain
<awygle>
also this crazy thing called a BasedVector which is a template class where one of the parameters is the starting index
<awygle>
so you can make an array that starts from 1 :P
<rqou>
yeah that's kinda weird
<rqou>
although in my rust code i like using lots of indices
<rqou>
makes lifetime management much easier
<awygle>
VPR does some stuff. i think the most interesting thing about it is the XML architecture file. i was looking at yosys just to see what's there, understand the internal representation, maybe reuse something or at least reduce impedance mismatch
<awygle>
yeah but you try to hide that from _users_ presumably
<rqou>
fortunately rust has really good generics
<rqou>
so you can make your indices all strongly typed
<rqou>
also, i personally would read yosys's json format rather than blif
<awygle>
also something i'm looking at, yeah
<awygle>
tbh i'm more interested in the internal data structures than the interchange format
<rqou>
yeah, that part of yosys is a little bit opaque
<rqou>
json is pretty close though
enriq has quit [Quit: My MacBook has gone to sleep. ZZZzzz…]
<awygle>
"As of this writing a Yosys VHDL frontend is in development." >_> <_<
<rqou>
it is?
<awygle>
because absolutely nobody dates anything ever, i have no idea when "as of this writing" is. it looks like a loooooooong time ago
enriq has quit [Quit: My MacBook has gone to sleep. ZZZzzz…]
test123456 has quit [Remote host closed the connection]
test123456 has joined ##openfpga
test123456 has quit [Max SendQ exceeded]
test123456 has joined ##openfpga
test123456 has quit [Remote host closed the connection]
test123456 has joined ##openfpga
enriq has joined ##openfpga
MrY has joined ##openfpga
test123456 has quit [Ping timeout: 246 seconds]
enriq has quit [Quit: My MacBook has gone to sleep. ZZZzzz…]
awygle_m has quit [Read error: Connection reset by peer]
awygle_m has joined ##openfpga
MrY has quit [Quit: Leaving]
digshadow has quit [Quit: Leaving.]
theMagnumOrange has quit [Ping timeout: 240 seconds]
digshadow has joined ##openfpga
theMagnumOrange has joined ##openfpga
enriq has joined ##openfpga
Hootch has quit [Quit: Leaving]
enriq has quit [Quit: My MacBook has gone to sleep. ZZZzzz…]
enriq has joined ##openfpga
enriq has quit [Client Quit]
enriq has joined ##openfpga
enriq has quit [Quit: My MacBook has gone to sleep. ZZZzzz…]
enriq has joined ##openfpga
test123456 has joined ##openfpga
enriq has quit [Quit: My MacBook has gone to sleep. ZZZzzz…]
enriq has joined ##openfpga
awygle_m has quit [Remote host closed the connection]
awygle_m has joined ##openfpga
enriq has quit [Quit: My MacBook has gone to sleep. ZZZzzz…]
jhol has joined ##openfpga
enriq has joined ##openfpga
enriq has quit [Client Quit]
specing has quit [Ping timeout: 246 seconds]
<pie__>
theres really only one thing i dislike about attempting to fix laptops
<pie__>
all the screwing
<rqou>
better than plastic clips :P
<awygle_m>
I am not very mechanically inclined but I find they never seem to go back together as solidly as before I open them
<pie__>
thats also a thing
<pie__>
also all the differnt types of screws and the one (two :P) you accidentally leave out
<pie__>
but i htink i solved that this time because i had some of those chinese compartmentalized electronics parts boxes laying around
<pie__>
kept notes as i went
<pie__>
we'll see how it goes lol
specing has joined ##openfpga
<pie__>
though i might just call my friend and asks if he wants me to even bother trying to put it back together since i got the data off and cant otherwise fix it
<pie__>
crap i just noticed that model is off by a letter though...
<pie__>
i mean maybe it would fit the machine but heck knows