<pie_>
if a really old laptop doesnt post at all or anything (black screen asus a6000) could that mean the cmos is dead?
<pie_>
for some dumb reason the cmos batt is always fucking inaccessible on laptops ;_;
<jn__>
usually they complain about that
<jn__>
do the LEDs blink?
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<pie_>
theres one led that has a light bulb on it that turns green and then turns off after about 3 seconds
<pie_>
everything else is off
<pie_>
the battery light is orange but ive also tried it without the battery
<pie_>
the cd drive makes some power on noises then the machine turns off
<jn__>
hmmmmm, is the RAM ok?
<pie_>
idk
<pie_>
idk how i would be able to check
<pie_>
bad ram stopping POST though? :C
<pie_>
wel not even POST, the screen shows nothing
<pie_>
i removed both ram modules, same behaviour, no beep, nothing, just the ?power? light being on for a couple seconds and the cd drive noise
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<pie_>
do old IDE looking laptop drives actually use ide connectors so i can use my adapter to save the data or is this something else?
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<openfpga-github>
yosys/rmports 3dd7f42 Andrew Zonenberg: opt_rmports: Fixed incorrect handling of multi-bit nets
<openfpga-github>
yosys/rmports 66aac06 Andrew Zonenberg: Removed commented out debug code
<openfpga-github>
yosys/rmports cca3cb5 Andrew Zonenberg: Added opt_rmports pass (remove unconnected ports from top-level modules)
<openfpga-github>
[yosys] azonenberg created rmports (+5 new commits): https://git.io/v77pb
<qu1j0t3>
pie_: There is a smaller format IDE connector for laptop drives.
<qu1j0t3>
pie_: & that connector is on things like my NewEgg IDE/USB adapter
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<openfpga-github>
[yosys] azonenberg created countfix (+13 new commits): https://git.io/v77h2
<openfpga-github>
yosys/countfix 0036de1 Andrew Zonenberg: Moved GP_POR out of digital cells b/c it has delays
<openfpga-github>
yosys/countfix 56bce99 Andrew Zonenberg: Improved cells_sim_digital model for GP_COUNT8
<openfpga-github>
yosys/countfix 23fddbe Andrew Zonenberg: Refactored GreenPAK4 cells_sim into cells_sim_ams and cells_sim_digital
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<azonenberg>
Hmm i screwed something up, that second branch includes the changes from the first one
<azonenberg>
Welp
<azonenberg>
I'll just let him merge rmports first :p
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<openfpga-github>
[yosys] azonenberg force-pushed countfix from 69448d4 to 348acbd: https://git.io/v77j5
<openfpga-github>
yosys/countfix 60dd5db Andrew Zonenberg: Moved GP_POR out of digital cells b/c it has delays
<openfpga-github>
yosys/countfix f55d4cc Andrew Zonenberg: Improved cells_sim_digital model for GP_COUNT8
<openfpga-github>
yosys/countfix fe3a932 Andrew Zonenberg: Refactored GreenPAK4 cells_sim into cells_sim_ams and cells_sim_digital
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<openfpga-github>
[yosys] azonenberg pushed 1 new commit to rmports: https://git.io/v75fc
<openfpga-github>
yosys/rmports 1a6a23f Andrew Zonenberg: Renamed opt_rmports pass to rmports
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<openfpga-github>
[yosys] azonenberg pushed 1 new commit to rmports: https://git.io/v75f1
<openfpga-github>
yosys/rmports d5e5bba Andrew Zonenberg: Updated Makefile to reflect opt_rmports being renamed to rmports
<openfpga-github>
[yosys] azonenberg pushed 1 new commit to rmports: https://git.io/v75UY
<openfpga-github>
yosys/rmports bd2ac68 Andrew Zonenberg: rmports now works on all modules in the design, not just the top.
<openfpga-github>
[yosys] azonenberg pushed 1 new commit to rmports: https://git.io/v75Un
<openfpga-github>
yosys/rmports 0ee27d0 Andrew Zonenberg: ProcessModule is no longer virtual (why was it in the first place?)
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<openfpga-github>
[yosys] azonenberg pushed 1 new commit to rmports: https://git.io/v75IO
<openfpga-github>
yosys/rmports 15e41d6 Andrew Zonenberg: rmports: Now remove ports from cell instances if we optimized them out of that cell
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<openfpga-github>
[yosys] azonenberg created jsoniofix (+1 new commit): https://git.io/v75qo
<openfpga-github>
yosys/jsoniofix 366ce87 Robert Ou: json: Parse inout correctly rather than as an output
<openfpga-github>
[yosys] azonenberg created abcfnames (+1 new commit): https://git.io/v75qQ
<openfpga-github>
yosys/abcfnames 9a64ba3 Robert Ou: abc: Allow +/ filenames in the abc command
<openfpga-github>
[yosys] azonenberg created crtechlib (+2 new commits): https://git.io/v75mJ
<openfpga-github>
yosys/crtechlib 78fd24f Robert Ou: coolrunner2: Add INVERT parameter to some BUFGs
<openfpga-github>
yosys/crtechlib 1e3ffd5 Robert Ou: coolrunner2: Add FFs with clock enable to cells_sim.v
<azonenberg>
Welp, i now have five pull requests out to clifford
<azonenberg>
and that isn't even all of our recent work, but i want to get these taken care of first
<enriq>
do we have the 64 already :)
<azonenberg>
No, this is all reformatting existing code to merge with upstream
<azonenberg>
The 64 is going to require hands-on lab work in the chem room at work
<azonenberg>
Which won't happen for at least a month b/c I have two weeks of vacation starting tomorrow, followed by two weeks on site with a client and thus no access to our lab
<enriq>
yes yes, just kidding and putting pressure
<enriq>
besides the xbox board, and openfpga (once it works for the 64) which other software would i need
<enriq>
and hardware
<azonenberg>
You'd need a jtag programmer of some sort, plus some software that works with it to program the 2c64a
<enriq>
my list says 1) an FT232 based usb-jtag dongle, 2)
<azonenberg>
xc3sprog, i think, should work with any ft232 based jtag board
<enriq>
it reads the jed? no I guess, I need the mapper
<enriq>
ah it does
<enriq>
I'm confused because I thought the programmer would need to understand the internal disposition of stuff inside the sillicon
<enriq>
oh it supports coolrnner ii :)
<azonenberg>
The programmer hardware is dumb, it just takes data the software gives it and spits it out
<azonenberg>
The software has to do the jed-to-jtag remapping
<enriq>
wasn't the jed "logical"
<enriq>
if I write the jed as per your notes (for a 32)
<enriq>
I just feed that with xc3prog?
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<azonenberg>
Yes, the jed is logical
<azonenberg>
what i meant is, somewhere it has to get remapped to physical addressing
<azonenberg>
and i think xc3sprog does that
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<openfpga-github>
[yosys] azonenberg created recover_adder (+10 new commits): https://git.io/v753c
<openfpga-github>
yosys/recover_adder 4641f1f Robert Ou: recover_adder_core: Implement the $alu generation
<openfpga-github>
yosys/recover_adder abae7f6 Robert Ou: recover_adder_core: Generate $add/$sub in the simple case...
<openfpga-github>
yosys/recover_adder 24cbc32 Robert Ou: recover_adder_core: Initial commit...
<openfpga-github>
[yosys] azonenberg pushed 1 new commit to recover_adder: https://git.io/v7535
<openfpga-github>
yosys/recover_adder 30d9fbc Andrew Zonenberg: Renamed recover_adder files from .cpp to .cc to fit with overall project file naming
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<azonenberg>
ok this is about as far as i can go, the merging is gonna become a big pain in the butt if i try to do everything at once
<azonenberg>
Gonna wait until this stuff gets merged i think
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<openfpga-github>
[yosys] azonenberg pushed 9 new commits to master: https://git.io/v75Gu
<openfpga-github>
yosys/master ce3a66d Andrew Zonenberg: Merge remote-tracking branch 'origin/crtechlib'
<openfpga-github>
yosys/master d2a4ed2 Andrew Zonenberg: Merge remote-tracking branch 'origin/countfix'
<openfpga-github>
yosys/master 3d757a5 Andrew Zonenberg: Merge remote-tracking branch 'origin/abcfnames'
<openfpga-github>
[yosys] azonenberg pushed 2 new commits to master: https://git.io/v75GP