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00:05
<
rqou >
also, neo geo cartridges are nuts :P
00:05
<
rqou >
they have something like 5 different parallel busses
00:07
<
rqou >
azonenberg_work: do you know how long a s6 takes to boot?
00:09
<
rqou >
alternately, how long does a gp4 take to boot? worst case i can use a gp4 to supply vectors and an infinite loop until the real fpga boots up :P
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00:59
<
azonenberg_work >
rqou: re s6 boot time
00:59
<
azonenberg_work >
what density
00:59
<
azonenberg_work >
and what boot media?
01:02
<
azonenberg_work >
you have a fixed latency of maybe 30 ms (datasheet says it can be as fast as 5) for power-on reset
01:02
<
azonenberg_work >
Then the boot time depends on the bitstream size, bus width, and clock rate
01:03
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01:03
<
azonenberg_work >
Fast: xc6slx9 (2.7 Mbits), max SPI clock rate (50 MHz), x4 bus width gives 2.7 Mb / 200 Mbps = 13.5 ms
01:04
<
rqou >
that's still pretty slow
01:04
<
rqou >
what's the boot time of a gp4/coolrunner-ii like?
01:04
<
azonenberg_work >
Slow: xc6slx150t (34 Mbits), slow SPI clock rate (2 MHz), x1 bus width gives 34 Mb / 2 Mbps = 17 sec
01:04
<
azonenberg_work >
:p
01:05
<
azonenberg_work >
artix can boot faster, i think
01:06
<
rqou >
but i need a part that boots before the host console boots
01:06
<
rqou >
which never seems to have been clearly documented how long that takes
01:07
<
azonenberg_work >
7 series... 10 to 35 ms POR time, then say an xc7a25t is 99 Mb
01:07
<
azonenberg_work >
9.9*
01:09
<
azonenberg_work >
So probably slower, but i think the fmax is higher
01:09
<
azonenberg_work >
The config time for an xc2c32a is only 50 us
01:10
<
azonenberg_work >
so waaaaay faster
01:11
<
azonenberg_work >
slg46620 is in between, 1.4 ms typical regardless of Vdd
01:12
<
rqou >
huh that's pretty slow
01:12
<
azonenberg_work >
yes, i think i know why
01:12
<
rqou >
sense amps? :P
01:12
<
azonenberg_work >
spartan6: 16-bit config datapath, very deep memory topology
01:13
<
azonenberg_work >
coolrunner: very wide and shallow config datapath (260 bits x 48 rows)
01:13
<
azonenberg_work >
Then greenpak is a bit different because they're using a standard TSMC 180nm NVM IP
01:13
<
azonenberg_work >
I suspect it's byte wide :p
01:14
<
azonenberg_work >
By 256 rows
01:14
<
azonenberg_work >
The physical die layout is 8 banks of 128 bits each, half above and half below a central spine
01:15
<
azonenberg_work >
Each bank is 32 cells wide by 5 bits high, i guess there's some parity or ecc or something in the array
01:15
<
azonenberg_work >
and of course, efuse is not exactly known for high speed compared to other kinds of memory
01:16
<
rqou >
hey, do you know what technology ice40 NVCM is?
01:16
<
azonenberg_work >
No, i have one on my bench but it isnt decapped
01:16
<
rqou >
it's not floating gates nor antifuse-in-vias
01:16
* azonenberg_work
is stretched very thin
01:16
<
azonenberg_work >
Guessing silicide electromigration efuse
01:16
<
azonenberg_work >
But i have no data to support that
01:17
<
azonenberg_work >
Could also be SONOS
01:17
<
azonenberg_work >
but that's normally reprogrammable so i doubt it
01:17
<
azonenberg_work >
silicide electromigration can be done with few if any additional masks vs flash needs a lot
01:17
<
azonenberg_work >
so makes sense for cost optimized parts
01:17
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01:17
<
rqou >
lattice claims: "There are no ways known to Lattice Semiconductor to physically or electronically read the Non-
01:17
<
rqou >
Block RAM (BRAM) memory areas, or to otherwise extract digital information stored in NVCM
01:17
<
rqou >
Volatile Configuration Memory (NVCM), or to trace its path to the Configuration RAM (CRAM) or
01:17
<
rqou >
or CRAM memory areas."
01:18
<
rqou >
"The NVCM memory is programmed by slightly changing the insulating properties of the
01:18
<
rqou >
There is no change to the chemistry of the material itself - the same atoms remain in
01:18
<
rqou >
to changes in the chemical bonding in atomically sized regions of the gate dielectric.
01:18
<
rqou >
core transistor gate dielectric. These changes in conductivity are thought to occur due
01:18
<
azonenberg_work >
Huh
01:19
<
azonenberg_work >
Not familiar with any such memory, but NVM is not my area of expertise
01:19
<
rqou >
i bet it's still pwnable with the "tap the databus" technique that "dr. decap" seems to like a lot
01:24
<
azonenberg_work >
Yep
01:24
<
rqou >
actually seems to be more reliable than rom staining, just sayin' :P :P
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01:40
<
azonenberg_work >
lol
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01:45
<
rqou >
hmm "retro-compatible" nonvolatile-memory is ridiculously expensive
01:45
<
rqou >
unless you play some really crazy tricks, it has to be fram/mram
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02:11
<
awygle >
rqou: microsemi flash fpgas maybe? they claim to come up very quickly (essentially concurrent with the rail)
02:12
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02:19
<
azonenberg_work >
rqou: because nobody makes 5V silicon anymore :p
02:20
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02:22
<
qu1j0t3 >
lol, seems you are right.
02:48
<
azonenberg_work >
these days i consider 3.3V "high voltage"
02:48
<
azonenberg_work >
and i mostly work at 1.8 for my IO
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03:13
<
rqou >
no, even ignoring the voltage problem, parallel-bus nonvolatile memory is weird :P
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03:15
<
rqou >
azonenberg_work: 8am classes suck :P
03:16
<
azonenberg_work >
Lol
03:16
<
azonenberg_work >
8am "be at the client" sucks too
03:16
<
azonenberg_work >
especially when the customer is two time zones later than home
03:16
<
azonenberg_work >
i had to be at their office at 6am seattle time this morning
03:16
<
azonenberg_work >
after waking up at 4am seattle time
03:16
<
azonenberg_work >
:p
03:17
<
rqou >
hey, do you think yosys formal verification can handle stable combinatorial loops? :P
03:17
<
azonenberg_work >
Nope
03:17
<
azonenberg_work >
I'd only use it for pure sequential stuff
03:17
<
azonenberg_work >
with a single clock
03:18
<
rqou >
that won't work too well for my vaporware goal of "formally verified 6502 transistors to modern hdl"
03:18
<
rqou >
you need dynamic logic
03:18
<
rqou >
which can be turned into latches
03:18
<
rqou >
but now you need latches :P
03:38
<
rqou >
does anybody have any idea why visual 6502 is broken in just one of my browser profiles?
03:39
<
rqou >
clicking clicks in a random spot only in one of the profiles
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04:19
<
rqou >
whelp, i actually tested what happens if there is a logic loop when you try to use the yosys write_smt2 command, and it definitely fails
04:19
<
rqou >
it also cannot handle latches
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04:54
<
azonenberg_work >
rqou: poke to investigate the extract_reduce segfault i linked in ##yosys
05:17
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05:40
<
rqou >
azonenberg_work: er, "ERROR: Unimplemented counter clock source 6 (in COUNT14_0)"
05:40
<
rqou >
am i on the wrong version somehow?
05:40
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06:20
<
azonenberg_work >
Hmmm
06:20
<
azonenberg_work >
i should look into that
06:21
<
azonenberg_work >
doesnt seem to happen on mine, i'll check
06:21
<
azonenberg_work >
... in the morning
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13:15
<
openfpga-github >
yosys/master c0034f5 Clifford Wolf: Merge pull request #397 from azonenberg/gpak-libfixes...
13:15
<
openfpga-github >
yosys/master 8530333 Clifford Wolf: Add {get,set}_src_attribute() methods on RTLIL::AttrObject
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19:29
<
azonenberg_work >
rqou: ping
19:30
<
azonenberg_work >
What are your thoughts on rebasing azonenberg/yosys on top of current upstream?
19:31
<
rqou >
i wanted you to do that for a while :P
19:31
<
azonenberg_work >
Lol
19:31
<
azonenberg_work >
I'll try and do that when i get home from the client tonight then
19:31
<
azonenberg_work >
Do you know if anybody else is using our dev fork?
19:31
<
rqou >
the autobuilds build it
19:31
<
rqou >
but they do a clean checkout every time
19:32
<
rqou >
my personal policy has always been that dev forks can get rebased at any time without warning
19:33
<
azonenberg_work >
Ok, if we want to make that our policy then we can do that
19:33
<
rqou >
i don't know if you want to make that "our" policy
19:33
<
rqou >
e.g. i wouldn't do that on the openfpga repo
19:33
<
azonenberg_work >
well that is a more "stable" repo
19:33
<
azonenberg_work >
because it's the authoritative main repo of the project
19:33
<
azonenberg_work >
azonenberg/yosys is more of a prototyping-before-clifford-merges-it repo
19:34
<
azonenberg_work >
So i think the policy should be, no rebasing on the primary repo
19:34
<
azonenberg_work >
But it's allowed on dev forks of upstream projects
19:34
<
azonenberg_work >
or on e.g. a private dev branch within openfpga
19:34
<
azonenberg_work >
just not openfpga/master
19:34
<
rqou >
e.g. rqou/openfpga gets rebased all the time
19:34
<
rqou >
idk if you noticed :P
19:35
<
azonenberg_work >
I dont follow that fork much so no
19:35
<
azonenberg_work >
Anyway if we're in agreement i'll rebase it tonight
19:35
<
azonenberg_work >
Being 75 commits ahead of upstream with half of them being dummy merges is a bit much :p
19:37
<
rqou >
yeah, i don't get how people survive without rebase
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22:23
<
azonenberg_work >
ooook rebase time
22:23
<
azonenberg_work >
wish me luck
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22:45
<
rqou >
hey azonenberg_work guess what :P
22:45
<
azonenberg_work >
?
22:45
<
rqou >
ROS (robot operating system) has reinvented Yet Another build system
22:45
<
azonenberg_work >
Lool
22:45
<
rqou >
aren't build systems _fun_? :P
22:48
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22:50
<
pie_ >
doesnt ROS do a lot of weird sit
22:50
<
rqou >
it's fancy and academic?
22:50
<
rqou >
i don't think ros is any good either
22:51
<
pie_ >
ive only tried to help my friend debug something once
22:51
<
pie_ >
dont remember much about it exept for not being particularly impressed
22:51
<
pie_ >
but it did seem to work overall
22:51
<
pie_ >
or something
22:51
<
azonenberg_work >
rqou: ok this rebasing is going to be a giant pain in the neck
22:51
<
azonenberg_work >
do i really want to do this? :p
22:52
<
rqou >
git should automatically drop unneeded commits
22:52
<
azonenberg_work >
Thats not the issue
22:52
<
azonenberg_work >
the issue is, it's trying to apply my old unmerged changes and then undo them
22:52
<
azonenberg_work >
and i get merge conflicts each time
22:53
<
azonenberg_work >
Let me make a new branch and see what i can do...
22:53
<
rqou >
rebase -i and manually drop commits you don't like?
22:53
<
azonenberg_work >
i got a ways through that and it got painful
22:54
<
azonenberg_work >
Going to fix a few things so clifford can merge some of my other commits first
22:54
<
azonenberg_work >
All of the refactoring and cherrypicking is probably messing with things too
22:54
<
rqou >
oh damn 78 commits ahead
22:54
<
azonenberg_work >
Lol :p
22:54
<
azonenberg_work >
You know what i might do?
22:55
<
azonenberg_work >
First, fix some of my pending changes so clifford can merge my other refactoring
22:55
<
rqou >
just take clifford's master and cherry-pick unmerged changes?
22:55
<
azonenberg_work >
Yeah
22:55
<
azonenberg_work >
basically that
22:55
<
azonenberg_work >
Take his master, merge all of my feature branches, then cherry-pick whatever is left
22:55
<
azonenberg_work >
and call that my new master
22:55
<
azonenberg_work >
i think it'll be easier than trying to retcon all of my past history
22:58
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23:15
<
azonenberg_work >
grr this is going to be a pain in the butt either way
23:15
<
azonenberg_work >
let me try rebasing again...
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23:20
<
openfpga-github >
yosys/master 2dbff07 Andrew Zonenberg: Fixed undeclared "count" in GP_COUNT14_ADV
23:20
<
openfpga-github >
yosys/master d89939c Andrew Zonenberg: Fixed typo in error message
23:20
<
openfpga-github >
yosys/master b5deee6 Andrew Zonenberg: Fixed undeclared "count" in GP_COUNT8_ADV
23:21
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23:22
<
azonenberg_work >
I think it worked
23:25
<
rqou >
we're still 30 commits ahead?
23:25
<
rqou >
have you made sure we haven't dropped anything btw?
23:26
<
rqou >
azonenberg_work: you need to drop recover_reduce
23:26
<
rqou >
also, despite clifford not liking it, the PR for TFFs is missing a commit
23:28
<
openfpga-github >
yosys/master e90eb0d Andrew Zonenberg: extract_counter: Minor changes requested to comply with upstream policy, fixed a few typos
23:28
<
openfpga-github >
yosys/counter-extraction 634f18b Andrew Zonenberg: extract_counter: Minor changes requested to comply with upstream policy, fixed a few typos
23:29
<
azonenberg_work >
oh let me fix that
23:29
<
azonenberg_work >
i'm not gonna rebase recover_reduce out, ok? just delete it?
23:30
<
azonenberg_work >
it'll get squashed whenever we fully merge with upstream
23:31
<
rqou >
recover_reduce is already upstream
23:32
<
openfpga-github >
yosys/recover_tff 5fd9c2a Robert Ou: Fix bug loading libraries when they are already loaded
23:32
<
azonenberg_work >
Yes. but called extract_reduce
23:32
<
azonenberg_work >
so if we have recover as well that has to get removed
23:32
<
azonenberg_work >
no we're good
23:32
<
azonenberg_work >
so are we OK now?
23:32
<
azonenberg_work >
I have a full clone of our old history if we have to pull any work out of it
23:32
<
azonenberg_work >
But i think i got everything
23:32
<
rqou >
i thought clifford renamed recover to extract (so we can drop recover)
23:33
<
azonenberg_work >
Do we have recover in our current version?
23:33
<
azonenberg_work >
i thought i removed recover when extract got merged to mainline
23:33
<
azonenberg_work >
there might be an add-and-delete commit in our history
23:33
<
azonenberg_work >
but is it worth editing that out?
23:33
<
azonenberg_work >
it turns into a nop so when upstream merges the history will be sane
23:34
<
rqou >
i might be confused
23:34
<
rqou >
i see a commit adding it, but i think you remove it somewhere
23:34
<
azonenberg_work >
Yeah
23:34
<
azonenberg_work >
I removed it when clifford merged it to upstream
23:34
<
azonenberg_work >
somehow it didn't auto-remove when the merge happened
23:34
<
azonenberg_work >
and it still thinks it's a new commit
23:37
<
rqou >
manually squash?
23:37
<
azonenberg_work >
is it worth it?
23:37
<
rqou >
eh, maybe not
23:38
<
azonenberg_work >
It's not 78 commits ahead now
23:38
<
azonenberg_work >
so this is progress :p
23:39
<
azonenberg_work >
And we
*have* been doing a lot of stuff
23:40
<
openfpga-github >
yosys/recover_tff 6b7c585 Andrew Zonenberg: Merge branch 'recover_tff' of github.com:azonenberg/yosys into recover_tff
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23:58
<
azonenberg_work >
rqou: ok so i think i'm going to work on optimizing counters in extract_counters now
23:58
<
azonenberg_work >
Then probably figure out how to optimize counters that don't techmap to hard IP
23:58
<
azonenberg_work >
by extracting them in a separate step, followed by techmapping back to generic RTL