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<
rqou>
hey azonenberg_work can you give me access to your yosys repo like i mentioned?
<
openfpga-github>
yosys/master 36cf18a Clifford Wolf: Fix "read_blif -wideports" handling of cells with wide ports
<
openfpga-github>
yosys/master 26766da Clifford Wolf: Add a paragraph about pre-defined macros to read_verilog help message
<
openfpga-github>
yosys/master 3a8f6f0 Clifford Wolf: Add verilator support to testbenches generated by yosys-smtbmc
<
rqou>
alright, thanks
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<
rqou>
azonenberg_work: it seems to me that some of the things in the xilinx cpld library guide are incorrectly listed as macros/primitives
<
rqou>
FDDCPE is listed as a macro
<
azonenberg>
which is what again? dual edge flipflop with set and enable?
<
rqou>
whereas FDDCE is listed as a primitive
<
rqou>
FDDCPE should be dual-edge with set, reset, and enable
<
azonenberg>
That does sound funny, i wonder if they just do some remapping in XST or something
<
rqou>
i wonder if some of these combinations are busted
<
azonenberg>
Possible
<
rqou>
i'm guessing some of these combinations weren't possible on older families
<
azonenberg>
Totally possible
<
rqou>
and when coolrunner-ii got added they didn't correctly update the library manual (this is very xilinx)
<
rqou>
hmm, FDDCPE is listed as only supported on coolrunner-ii anyways
<
rqou>
might just be an error in the manual
<
azonenberg>
also possible that silicon does not properly handle simultaneous set/reset
<
azonenberg>
i.e. it's undefined
<
azonenberg>
and they add prioritization to them in a HDL wrapper so the result is well defined
<
rqou>
that doesn't seem to be what it says for FDCPE
<
rqou>
maybe the DDR versions are a bit more busted than we think?
<
rqou>
we should file these under "need to test more carefully"
<
azonenberg>
maybe?
<
azonenberg>
Would be funny if we found a silicon erratum
<
rqou>
seems pretty wtf to me
<
rqou>
this isn't particularly difficult to design
<
rqou>
i'm going to assume it's correct for now
<
rqou>
*correct in silicon, incorrect in the manual
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<
rqou>
azonenberg: is there a good way to test whether my cells_sim.v does the correct thing?
<
openfpga-github>
yosys/master 8eb5348 Robert Ou: coolrunner2: Add FFs with clock enable to cells_sim.v
<
openfpga-github>
[openfpga] rqou opened issue #106: Carefully test interaction between set/reset/enable/DDR on Coolrunner2
https://git.io/v70SY
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<
rqou>
wait, BTC split?
<
rqou>
damn, should have sold my coins :P
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