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<rqou>
whee, finally after bikeshedding and family politics, we can upgrade the HK flat from 1.5 working air conditioners (0.5 in bedrooms) to 2.5 working air conditioners (1.5 in bedrooms)
<rqou>
out of 5 total
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<openfpga-github>
[yosys] azonenberg pushed 4 new commits to master: https://git.io/vQO4l
<openfpga-github>
yosys/master 1f517d2 Clifford Wolf: Fix history namespace collision
<openfpga-github>
yosys/master c0ca994 Clifford Wolf: Store command history when terminating with an error
<openfpga-github>
yosys/master f6421c8 Clifford Wolf: Switched abc "clock domain not found" error to log_cmd_error()
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<openfpga-github>
[yosys] azonenberg pushed 1 new commit to master: https://git.io/vQOuw
<openfpga-github>
yosys/master cbdddc3 Andrew Zonenberg: greenpak4_counters: Changed generation of primitive names so that the absorbed register's name is included
<openfpga-github>
[openfpga] azonenberg pushed 1 new commit to master: https://git.io/vQOuy
<openfpga-github>
openfpga/master b53f2e2 Andrew Zonenberg: gp4par: Changed congestion metrics for better avoidance of congestion
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<openfpga-github>
[openfpga] azonenberg pushed 1 new commit to master: https://git.io/vQO2T
<openfpga-github>
openfpga/master 1d910aa Andrew Zonenberg: Timing analyzer is now aware of which cells are stateful, and won't report false combinatorial loops for stateful logic. No timing data for these blocks yet, though.
<openfpga-github>
[openfpga] azonenberg pushed 1 new commit to master: https://git.io/vQOa2
<openfpga-github>
openfpga/master 0fc9a9c Andrew Zonenberg: Refactoring: XC2C model now stores bitstream in block RAM for readbacks and only uses DFFs for device configuration