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<rqou> taking the bus like a pleb and I notice that China's services are awful at "usability"
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<azonenberg> rqou: so, lulzy idea
<azonenberg> if you want a fun POC||GTFO artile
<azonenberg> article*
<rqou> what?
<azonenberg> Make a coolrunner JIT :p
<rqou> wtf?
<azonenberg> modify my current emulator so it will translate the PLA AND/OR bits, and maybe the ZIA, from coolrunner native "opcodes" to shift register LUTs or similar
<azonenberg> or LUTRAMs
<azonenberg> dynamically build truth tables based on the bitstream
<rqou> lool
<rqou> goddammit azonenberg make xc2par work first :P
<azonenberg> lol i wasnt going to actually *do* it, at least not soon
<azonenberg> and i'm busy doing pcb deisgns for greenpak ptv characterization
<azonenberg> The point was more, it would be hilarious if you could make a JIT that turned coolrunner bitfiles into something the fpga could execute more efficiently
<rqou> that sounds totally possible
<azonenberg> i know
<azonenberg> i wanna do it, but not any time soon
<azonenberg> gotta get the baseline unoptimized emulator working first
<rqou> after doing par for the FPGA first :P
<azonenberg> Hey, its not like my hands arent full...
<rqou> anyways, I'm currently on the "pleb" bus again back into the city
<rqou> going to take the cross-border bus tomorrow to HK to visit M-Labs
<azonenberg> Say hi to sb0 for me
<azonenberg> and whitequark if they're in the lab (idk about current location)
<rqou> waiting for HK to finish their end of the Guangzhou-Shenzhen-Hong Kong high-speed rail
<rqou> (should be done in 2018)
<azonenberg> also, lol
<azonenberg> after over a year of dev work on the greenpak tools
<azonenberg> i am finally making a kicad footprint for the greenpak stqfn20
<rqou> lool
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<openfpga-github> [openfpga] azonenberg pushed 1 new commit to master: https://git.io/vQINg
<openfpga-github> openfpga/master b08ddd9 Andrew Zonenberg: Initial version of gp4-stqfn20 board. Still needs final review prior to signoff.
<azonenberg> Still have to do some tweaks, add silkscreen labels to the i2c header, etc
<azonenberg> but basically ready to go
<rqou> azonenberg: I just realized something
<rqou> we should gpg-sign certain openfpga commits
<rqou> e.g. the one I published xc2bit 0.0.1 from
<rqou> we should start setting up a policy for how we're going to do this
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<rqou> azonenberg: i just poked in ISE again
<rqou> "TestPin" in xbr.chp sounds very interesting
<rqou> huh, i just realized that my laptop was still stuck on sublime text 2
<rqou> and sublime text 3's download server is super slow in china (typical)
<openfpga-github> [openfpga] rqou pushed 1 new commit to master: https://git.io/vQLw2
<openfpga-github> openfpga/master 8f6b576 Robert Ou: xc2bit: Initial error handling refactor...
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<openfpga-github> [openfpga] rqou pushed 1 new commit to master: https://git.io/vQLX9
<openfpga-github> openfpga/master b2e80eb Robert Ou: xc2bit: Actually commit errors.rs file missing from last commit
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<azonenberg> rqou: there are lots of test pins mentioned in various data files
<azonenberg> including spartan3a
<balrog> azonenberg: btw I looked at the difference between spartan3 and spartan3a
<balrog> 3a is smaller
<azonenberg> The 3s50a is 22x21 tiles
<azonenberg> 462 total
<azonenberg> 1479 sites
<azonenberg> 34 types of primitive
<azonenberg> 28,786 pins
<azonenberg> and 671,428 pips
<azonenberg> (according to the XDL dump)
<balrog> aha
<balrog> datasheet says 3s50a has 1584 "equivalent logic cells" and 3s50 has 1728
<balrog> however this doesn't add up
<balrog> both have 16 rows and 12 columns in their CLB arrays
<azonenberg> How about multipliers?
<azonenberg> iirc that generation they counted dsp blocks in gate count
<balrog> the 3s50 has 192 CLBs, the 3s50a has 176
<balrog> 3s50: 4, 3s50a: 3
<balrog> they increased I/Os though
<azonenberg> interesting
<azonenberg> Oh
<azonenberg> Yeah the 3s50a isnt a full array
<azonenberg> thats why
<azonenberg> there's a cutout for the two DCMs
<azonenberg> i bet the 3s50 doesnt have DCMs
<azonenberg> or they're outside the CLB array
<balrog> the 3S50 also has two DCMs
<azonenberg> prob different layout
<azonenberg> 16*12 = 192
<balrog> both claim 16*12 :p
<azonenberg> https://siliconpr0n.org/archive/lib/exe/fetch.php?cache=&media=azonenberg:xilinx:xc3s50a:xc3s50a_active_bf_neo10x_3k.jpg
<azonenberg> the 3s50a has holes in the clb array for the dcms
<azonenberg> i didnt count how many were missing
<balrog> what's up with the empty areas on the right side?
<balrog> well, not really empty, but
<balrog> you see the structures I'm referring to?
<balrog> 3 of them
<balrog> those might be the multipliers
<balrog> that's kinda useless
<openfpga-github> [openfpga] azonenberg pushed 2 new commits to master: https://git.io/vQL9I
<openfpga-github> openfpga/master 18033e5 Andrew Zonenberg: Merge branch 'master' of github.com:azonenberg/openfpga
<openfpga-github> openfpga/master 4aee033 Andrew Zonenberg: Updated design after review
<openfpga-github> [openfpga] azonenberg pushed 1 new commit to master: https://git.io/vQL9m
<openfpga-github> openfpga/master 170a3ec Andrew Zonenberg: updated ignore
<azonenberg> Ok, greenpak stqfn-20 thermal test board ordered
* azonenberg off to work
<balrog> nice!
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<azonenberg_work> balrog: so the basic xc3s50a structure is
<azonenberg_work> (https://siliconpr0n.org/archive/lib/exe/fetch.php?cache=&media=azonenberg:xilinx:xc3s50a:xc3s50a_active_bf_neo10x_3k.jpg)
<azonenberg_work> io tiles on n/s/e/w of main array
<azonenberg_work> Unknown logic, most likely config/jtag, in the corners
<azonenberg_work> DCMs are the big cutouts just east/west of the centerline on the north side of the chip (with the big blue area)
<azonenberg_work> Just below the right hand DCM are the multipliers and BRAMs
<azonenberg_work> the BRAMs are the six dense arrays, two 9kbit arrays per BRAM (although in s3, unlke s6, the two arrays cannot be individually addressed)
<azonenberg_work> immediately left of the BRAM is some addressing logic
<azonenberg_work> then after that to the central spine are the multipliers and some routing logic driving the BRAM+MULT tile inputs (there's some shared douting and at the moment i dont fully understand that, i have to spend more time reading the datasheet)
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<balrog> azonenberg_work: I see
<balrog> hmm...
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