<azonenberg>
current json timing data export for one particular die i've been playing with
<azonenberg>
voltage corners only
<azonenberg>
(and 3.3V only)
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<digshadow>
rqou: sem is offline right onw
<digshadow>
its a bit awkward to use right now
<digshadow>
and last week I lent out my vacuum pump to another sem
<azonenberg>
digshadow: meanwhile i'm finally starting to get sem/fib access
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<openfpga-github>
[openfpga] azonenberg pushed 1 new commit to master: https://git.io/vH29X
<openfpga-github>
openfpga/master e1c9b44 Andrew Zonenberg: Began work on loading timing data from JSON
<openfpga-github>
[openfpga] azonenberg pushed 1 new commit to master: https://git.io/vH29y
<openfpga-github>
openfpga/master 9c33a81 Andrew Zonenberg: Fixed typo
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<openfpga-github>
[openfpga] azonenberg pushed 1 new commit to master: https://git.io/vH2Hr
<openfpga-github>
openfpga/master c014b81 Andrew Zonenberg: IOB now loads timing data from JSON correctly. gp4tchar now operates in "append" mode, adding timing data to existing file if present
<azonenberg>
also, i really have to optimize my test drive
<azonenberg>
right now i have 3200 JTAG transactions for every single delay measurement (100 averages, 32 taps eacH)
<azonenberg>
if i moved the delay tap logic into the FPGA, i could cut that down to 100 jtag transfers each
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<openfpga-github>
[openfpga] azonenberg pushed 1 new commit to master: https://git.io/vH27A
<openfpga-github>
openfpga/master 9be991e Andrew Zonenberg: Now measuring LUT delays
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<openfpga-github>
[openfpga] azonenberg pushed 1 new commit to master: https://git.io/vH25E
<openfpga-github>
openfpga/master 517fb32 Andrew Zonenberg: Now characterizing LUTs across 3.3V voltage range
<azonenberg>
Ok, that's enough for tonight
<azonenberg>
I have LUT, cross-connection, and I/O cell rising-edge-only propagation data
<azonenberg>
before i do anything else i need to massively optimize my data collection so it doesn't take 5 seconds or so per measurement
<azonenberg>
And add falling-edge propagation delay stuff
<azonenberg>
once i get that done i can start working on setup/hold time measurements
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<pie_>
azonenberg, just use some crappy scientific data format or a mysql database
<pie_>
"After I reported a few bugs in their datasheets they decided to skip the middleman and give me direct access to the engineer who writes their documentation so that I can get faster responses. " thats awesome :)
<pie_>
huh this is a year old eh
<lain>
time flies
<qu1j0t3>
pie_: A year old and still really inspiring
<cyrozap>
The same seller also has XC7K410T's for $400 each.
<pie_>
is fpga counterfeiting a thing
<lain>
some people will sell pulled & reballed fpgas as new
<cyrozap>
Possibly, but this seller has a flawless rating, so my guess is they're selling either stolen goods or ones that didn't pass all the QA checks.
<cyrozap>
Ah, yeah, that might be it, too.
<lain>
also I suspect people buying high-end FPGAs off ebay aren't likely to do thorough testing ;)
<lain>
but if they work at all that's a good sign :P
<lain>
I mean, at least that means they didn't just laser a different chip to say it's whatever fpga (which is common in counterfeiting)
<lain>
hm. you know, I never really thought about it, but I wonder if that's one of the reasons intel and other companies use goofy-ass bga footprints - if each chip has a unique footprint, it'd be a lot more effort to counterfeit
<lain>
vs. stuff using a typical full grid array where it could be any ol' 1mm pitch 400-ball chip, or etc
<pie_>
huh.
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<zino>
I wish Motorola had done that. Finding a non-fake 68060 is hard.
<rqou>
how fake is fake? totally different part or something like "hitachi's version, not an original motorola version?"
<rqou>
also, i thought 68ks were in a unique giant dip package?
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<zino>
Most of them are low-cost 060 lacking MMU and FPU relasered to be high-end 060s of a later revision. But some are re-labeled 040s-
<zino>
They come mostly in PGA-package with the same layout as 040.