<rqou>
azonenberg: you can come to Guangzhou and live like a "poor person" like I am doing now :P :P
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<azonenberg>
rqou: lol no :p
<azonenberg>
whitequark: are you around?
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<whitequark>
yeah
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<azonenberg>
whitequark: so i'm trying to debug the buildbot
<azonenberg>
it seems to be... acting up a bit
<azonenberg>
i just upgraded the host to stretch from jessie which might be part of the problem
<openfpga-github>
openfpga/master fca4f85 Andrew Zonenberg: Temporarily disable SLG46621 HiL tests because we don't have a dashboard test devkit yet
<openfpga-github>
openfpga/master f597239 Andrew Zonenberg: Moved tri-state buffers to parent module rather than XC2CDevice. RRefactoring: renamed some variables
<openfpga-github>
[openfpga] azonenberg pushed 4 new commits to master: https://git.io/vQfti
<openfpga-github>
openfpga/master 9687318 Andrew Zonenberg: Explicitly specify bit width to avoid warning
<whitequark>
rqou: [/var/buildbot/slave-debian-stretch-amd64/openfpga/openfpga/src/vendor/hidapi/linux/hid.c:237]: (warning) %x in format string (no. 1) requires 'unsigned int *' but the argument type is 'int *'.
<rqou>
wtf
<rqou>
is this the rewrite PR or master?
<whitequark>
master...
<openfpga-github>
[openfpga-buildbot-config] whitequark pushed 1 new commit to master: https://git.io/vQfYd
<whitequark>
/var/buildbot/slave-debian-stretch-amd64/openfpga/openfpga/src/xbpar/PAREngine.cpp:51:27: runtime error: unsigned integer overflow: 15726070495360670683 * 6364136223846793005 cannot be represented in type 'unsigned long long'
<whitequark>
was the buildbot out of commission or what
<rqou>
whitequark: is this building with clang or GCC? I don't recall getting that warning with GCC (but then GCC sucks at warnings)
<whitequark>
clang
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<rqou>
alright, _finally_ have a China SIM
<rqou>
apparently my father was blacklisted by Unicom because he owed them money
<balrog>
rqou: and that applied to you?
<balrog>
rqou: also how are you dealing with the firewall?
<rqou>
my father was getting the sim under his name
<rqou>
for the firewall, currently no workaround on my phone
<rqou>
on my computer I was testing ssh over obfs4proxy and it seemed to work
<rqou>
amazingly, DPI seems to flag direct ssh tunnels nowadays
<balrog>
have had to deal with the internet at a high school that blocks ssh tunnels
<rqou>
nah, my school isn't that competent
<rqou>
the diglossia in Guangzhou is so weird when I actually experience it
<azonenberg>
whitequark: yes the buildbot was down
<azonenberg>
basically, i stole the devkits for other stuff since i didn't have enough
<azonenberg>
silego just mailed me a few more
<azonenberg>
it was probably bottlenecking before waiting for HiL tests to run or somethin
<azonenberg_work>
Also, heading out to the garage to play reworkctf more
<pointfree>
Saving the planet. One greenpak at a time...
<azonenberg_work>
lol
* azonenberg_work
facepalms
<azonenberg_work>
ordered a new board from digikey
<azonenberg_work>
parts for a new board*
<azonenberg_work>
forgot to get a connector for it
<azonenberg_work>
Welp
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<rqou>
azonenberg: you mentioned you liked d(boonies)/dt? try China :P
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<rqou>
why are there a bajillion proxy protocols?
<rqou>
firewall circumvention tools are all shit
<azonenberg>
rqou: b/c the GFW keeps evolving
<azonenberg>
and you have to keep using protocols it hasn't seen before
<rqou>
no, I'm talking about very basic problems like "I need yet another program to make my HTTP-proxy-speaking device (phone) talk to my SOCKS-speaking server (ssh client)"
<lain>
just use openvpn
<lain>
:P
<rqou>
OpenVPN is a) detected and b) doesn't work great on Android
<lain>
it works fine on android in my experience
<lain>
I'm surprised it's detected -- is that even with tcp over port 443?
<lain>
I mean, I know don't tunnel tcp over tcp but...
<rqou>
apparently even bare ssh tunnelling gets detected nowadays
<lain>
whee
<lain>
use a satellite connection, clearly
<rqou>
so right now I have a clusterfuck of phone --HTTP proxy--> Polipo --> ssh --> obfs4proxy
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<pointfree>
cyrozap, et al.: PSoC5LP sample config #0: https://github.com/azonenberg/openfpga/wiki/UDB-&-Routing-Examples#sample-config-0-route-from-portpin-22-to-portpin-21-blue-led-through-the-dsi
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<pointfree>
I think sample config #1 should be an OR, AND, or XOR gate entirely inside the DSI with no PLD's involved.
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<openfpga-github>
openfpga/master 3995978 Andrew Zonenberg: XC2C model: implemented PLA AND array
<openfpga-github>
[openfpga] azonenberg pushed 1 new commit to master: https://git.io/vQUUU
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<openfpga-github>
[openfpga] azonenberg pushed 2 new commits to master: https://git.io/vQUXq
<openfpga-github>
openfpga/master 73a1180 Andrew Zonenberg: Refactoring: Moved XC2C bitstream into separate source file vs having it in Device module
<openfpga-github>
openfpga/master 78cf6ff Andrew Zonenberg: Initial version of OR array. Not yet hooked up.
<azonenberg>
rqou: Implemented PLA AND and OR models for the coolrunner emulator
<azonenberg>
not fully tested on the OR, the AND is done
<rqou>
nice
<azonenberg>
and seems to be good
<rqou>
I should get out of bed :P
<azonenberg>
13844 FF (10% of 7a100t)
<azonenberg>
exactly 16384 LUTs, lol - 25% of the chip
<azonenberg>
5469 slice (34%)
<azonenberg>
Still have to do macrocells, clocks, etc
<azonenberg>
The macrocell will take some work due to the way the FPGA clock tree is built
<rqou>
I've never looked into the 7-series clock tree
<azonenberg>
What i may have to do is have multiple macrocell FFs
<rqou>
I know it has stuff like BUFH that is new
<azonenberg>
and then mux the GCK0 FF, GCK1 FF, GCK2 FF depending on which bit i used
<azonenberg>
BUFH is not new
<azonenberg>
however, in 6 series the BUFH did not have a clock enable
<azonenberg>
in 7 it does
<azonenberg>
BUFHCE is new
<rqou>
eh, a bunch of my previous experience was with s3e