<rqou>
somehow my responses are turning into servfails somewhere between my server and my client
<pie_>
ill have to find out where theyre from tomorro
<pie_>
rqou, magic
<pie_>
anyway, gnight guys
<azonenberg_hk>
So after some thinking
<azonenberg_hk>
I am splitting the DCMP into two primitives GP_DCMP and GP_PWM
<azonenberg_hk>
with slightly different sets of config
<cyrozap>
Hey, pointfree, do you know off the top of your head whether the PLDs in a UDB share input terms? My gut says "probably", but I can't remember where in the documentation where to find that out for certain.
<cyrozap>
I'm currently making my Go UDB-parsing code into a UDB-to-Verilog converter, complete with macrocell functions and (maybe) datapath instantiation. It's not nearly as difficult as I thought it would be, especially once I stopped trying to parse the config memory dump and print Verilog at the same time.
<cyrozap>
s/where to find that out/I can find that out/
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<pointfree>
cyrozap: are you asking if the PLD's share the OR array? I would think not, because the OR terms are separated by PLD. Also, PSoC Creator limits LUT's to 5 input terms last I checked.
<cyrozap>
pointfree: No, I want to know if IT0 on PLD0 == IT0 on PLD1. i.e., is the input to the UDB 24 bits wide or only 12?
<pointfree>
cyrozap: you might be right because PSoC Creator allows a maximum of 5 inputs and 8 outputs for a LUT.
<pointfree>
To confirm, one would have to build the project and check the .route file to see if these PLD outputs are associated with the same UDB. Probably they are.
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<whitequark>
azonenberg_hk: sup
<whitequark>
just got UDP loopback working in smoltcp
<whitequark>
well, except that it has invalid ethernet FCS but who cares about minor details like not actually being able to receive those packets
<whitequark>
so now going to grab some food and depart
<azonenberg_hk>
whitequark: Lol
<azonenberg_hk>
Important details
<azonenberg_hk>
Got an ETA?
<whitequark>
let's see, 90 minutes from now sounds about right
<rqou>
who here knows how to systemd?
<whitequark>
rqou: I do
<azonenberg_hk>
whitequark: Ok
<whitequark>
dpkg --purge systemd
<rqou>
how do i fix "Excess arguments"?
<lain>
xargs?
<azonenberg_hk>
whitequark: i'm about to head down to the gym in the hotel, will wait for you in the lobby after i finish up
<azonenberg_hk>
If you don't see me in the lobby, the gym is down the stairs just right of the escalator
<lain>
(I have no idea)
<azonenberg_hk>
whitequark: and dont forget your power cable this time :p
<rqou>
apparently you will get a mysterious "Excess arguments" error if you accidentally use "systemd" instead of "systemctl"
<rqou>
thanks poeterringware
<azonenberg_hk>
lol
<azonenberg_hk>
systemd is one of those projects whose bus factor is way larger than i'd like
<azonenberg_hk>
:p
<azonenberg_hk>
Can we just get one lucky alien abduction or something?
<rqou>
aaaargh my iodined is still not working
* rqou
rages
<rqou>
i've been working on this for hours
<rqou>
mostly because iptables is dumb
<rqou>
and apparently the iptables "BM" string compare algorithm just sometimes mysteriously fails
<rqou>
KMP seemed to work
<rqou>
heh this last one was me footgun-ing myself with iptables :P
<rqou>
i forgot to allow ssh
<mtp>
i hate dealing with iptables directly; the only sane wrapper i've found for it is ferm
<rqou>
i currently don't use wrappers because they all suck too
<mtp>
i only have two boxes where i have to think about iptables
<mtp>
working to make that 0
<azonenberg_hk>
i use shorewall b/c it seems like the least bad of the bad optoins
<rqou>
alright, finally finally have my iodine working
<azonenberg_hk>
i need to write an fpga-based router, lol
<azonenberg_hk>
something with a sane config infeterce
<rqou>
(ip over dns / captive portal bypass in cause you're not aware)
<mtp>
my router at home runs openbsd
<mtp>
most of my cloud shit runs freebsd
<rqou>
my router runs my housemate's formerly-dogfooding meraki equipment
<mtp>
both of which have pf, which is a pleasure to use
<rqou>
gotta hope there's no backdoor there
<rqou>
:P
<rqou>
apparently only the "real" cisco stuff gets backdoored and photographed :P
<azonenberg_hk>
Lol
<azonenberg_hk>
Yeah i have some secondhand cisco switches
<azonenberg_hk>
i dont fully trust them and would love to replace them with a custom fpga unit
<azonenberg_hk>
i have the mac address table and phy interface stuff written already
<azonenberg_hk>
just never had time to buckle down and do the switch fabric itself
<mtp>
pf is great because it's transactional and the state-tracking isn't opaque as shit (-p tcp --syn -m ctstate --ctstate NEW is just the goddamn default), and probably some other reasons i forget
<rqou>
eh, my firewall on my server is hybrid stateful/stateless
<rqou>
:P
<rqou>
that's why getting iodine to work took hours
<pcbhdl-github>
pcbhdl/master 736fd9c whitequark: setup.py: use more precise package names.
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<whitequark>
rqou: wtf is happening in HK tonight
<whitequark>
there's a police helicopter circling above tai po tsai for a hour and like six police cars on the way to it that do random checks
<pie__>
i bet theres some ghost in the shell shit going on
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<pie__>
i think somone told me that its generally fpgas pushing technology nodes before processors?
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<pie__>
ok, problem 2, how do i translate all these into hungarian
<dingbat>
pie__: not sure about that, virtex ultrascale is 20nm, whereas mobile phones have 14nm, skylake-Y and kabylake-Y are 14nm, and AMD has 14nm GPUs.
<dingbat>
oh and broadwell-Y/U IIRC
<pie__>
ah, well, ok then
<dingbat>
although, that said, i'm not sure about the next gen stuff that Xilinx/Altera is working on, their generally quite secretive about that kind of stuff
<pie__>
kinda funny because intel has altera now
<pie__>
(iirc?)
<dingbat>
pie__: correct. The hope is that we might see FPGAs that are pin compatible with some processor sockets, which allows cheap OTS mobos to function as FPGA dev boards, which would be cool
<pie__>
huh. that would be neat
<pie__>
we could finally get rid of those damn backdoored intel cpus :P
<felix_>
well, the management engine is in the chipset, not the cpu... ;P
<qu1j0t3>
dingbat: oh yeah that would be nice.
<pie__>
"Question: For the same IC fab, if the die yield is 90%, wafer and packaging yield
<pie__>
are 100%, and capacity is 20,000 wafers per month, what is the total
<pie__>
profit margin per month? (The hardest math in this book.)"
<pie__>
- Hong Xiao, introduction to semiconductor manufacturing
<pie__>
xD
<pie__>
"Question: If the die yield for every processing step is 99%, and there are 500 processing steps for IC fabrication, what is the overall die yield?
<pie__>
Answer: The overall die yield is 99% × 99% for 500 times, which equals 0.99500 = 0.0066 = 0.66%."
<pie__>
the lesson being you have to have very reliable steps