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<azonenberg> rqou: back
<azonenberg> So, PTC is known
<azonenberg> PTA/PTB/CTx are at unknown locations
<azonenberg> We also do not know enough about the macrocell bits to do anything clocked, you are correct
<azonenberg> I stopped at combinatorial logic because I couldn't synthesize anything
<azonenberg> due to lack of yosys support
<azonenberg> PTC is a fixed pterm
<azonenberg> There are a few non-magic pterms
<azonenberg> that are just general logic and dont do anything special
<azonenberg> rqou: my thought was to use xbpar to place each pterm separately
<azonenberg> With graph labels to specify PTA, PTB, PTC, etc
<azonenberg> as well as one for "any pterm"
<azonenberg> then have separate labels for macrocells, iobs, etc
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<cyrozap> nats`, rqou: It's easy to flash 6- and 7-series FPGAs with OpenOCD now. I have an example in the note here: https://github.com/cyrozap/openocd-xilinx-loader#openocd-xilinx-loader
<cyrozap> nats`, rqou: Also you can get super cheap CoolRunner dev boards now thanks to them being used on Xbox 360 modchips: http://www.ebay.com/itm/XILINX-CoolRunner-II-FPGA-CPLD-XC2C64A-Core-Module-Mini-DEV-Development-XBOX360-/182065717850
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<rqou> cyrozap: i need a xc2c32a, not a 64a
<rqou> i already have access to a 64a
<azonenberg> rqou: i made a board a while ago with every coolrunner from 32 to 256 macrocells
<azonenberg> and dip switches to put one or any set in the scan chain
<azonenberg> diamondman has one
<azonenberg> i have one
<azonenberg> i made 3, dont remember if i have the 3rd or not
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<rqou> azonenberg: i just realized that you don't strictly need to steal an or gate to route between fbs
<rqou> you can also route PTC into the ZIA
<rqou> but you can get screwed if somehow you simultaneously need PTC as both a clock and to cross the ZIA
<rqou> and you are out of sum terms
<rqou> idk how you would do that :P
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<rqou> hey, who here knows how to read $sop cells?
<rqou> why is clifford not awake yet? :P
<openfpga-github> [openfpga] rqou opened issue #64: Missing libertine.sty hangs build indefinitely https://git.io/vMTZW
<openfpga-github> [openfpga] rqou closed issue #64: Missing libertine.sty hangs build indefinitely https://git.io/vMTZW
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<openfpga-github> [openfpga] rqou pushed 1 new commit to master: https://git.io/vMTgr
<openfpga-github> openfpga/master 1b4f7ed Robert Ou: gp4par: Fix copy/paste error in error message
<openfpga-bb> build #49 of openfpga is complete: Success [build successful] Build details are at https://openfpga-dashboard.antikernel.net/builders/openfpga/builds/49
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<rqou> azonenberg: "that file" interestingly lists some bare die variants that the datasheet doesn't have
<rqou> there's also a mystery "CV64" pinout
<mithro> rqou: I regularly use openocd with Xilinx FPGAs if you need any help with that
<rqou> later i'll annoy you about that
<balrog> clifford wolf's talk is now!
<felix_> that works well; you probably need to build openocd from the source though; last time i wanted to use it, the release evrsion didn't include the patches for that support
<balrog> felix_: I haven't been able to track you down yet
* felix_ is currently at the openfpga table
<balrog> I'm at clifford's talk
<felix_> ok
<balrog> probably will walk by there around 19:30
* felix_ is the guy with a macbook with a coreboot sticker on it
<felix_> ok; see you then
* felix_ will watch the talks he's interested in after the congress is over
<jhol> felix_ is there anyone at the table who would like to test a kernel driver ;-)
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* felix_ just needs to be motivated to do that. i already had built a kernel, but then i upgraded the vm to fedora 25 and the parallels client extensions seem currently not to work with systems using wayland
<jhol> yuck
<jhol> I suppose there will be a way to bring back the x server in fedora
<felix_> what that happened i also dind't have access to my main backup storage any more
<felix_> well, i threw the broken vm away and did a fresh f24 install in a new vm
<jhol> such a pain
<felix_> yep
<jhol> this is why I wouldn't use macos
<felix_> rqou: "openocd -f board/kc705.cfg -c init -c “pld load 0 bitstream.bit” -c exit"
<felix_> jhol: well, linux on the desktop is still in a rather sad state, so i strongly prefer the osx gui :/
<jhol> works for me :)
<felix_> doesn't the design you're simulating has to be gpl too then?
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<balrog> felix_: only if you release it that way?
* felix_ is not a lawyer, so he just doesn't use any gpl components in any project that won't be released under the gpl
<rqou> offtopic: my janky adapters are causing a potential difference between my laptop body and the metal rim of the table
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<felix_> balrog: i'll be at the coreboot table for some time now
<balrog> I'll head over after this talk slot
<pie_> o/
<pie_> i didnt come today :/ hoping to get my cold under control a bit
<qu1j0t3> pie_: you sound like patient zero out of a Michael Crichton novel, just sayin
<pie_> lol
<pie_> qu1j0t3, "itsnot as bad as it sounds@
<pie_> "
<qu1j0t3> :)
<qu1j0t3> that's good
<qu1j0t3> u need to soak up the convention fun that I cannot :/
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<nats`> anybody played with parallela board ?
<nats`> I have one since.... fwwwwww long time
<nats`> and I never played with it
<nats`> I'm not even sure anybody played with the parallela chip
<zino> There is Jtagulator. Only thing I know of that contains the Parallella.
<nats`> what do you mean ?
<zino> I took your comment literally as in "I don't know anyone that uses paralella" and brought up the Jtagulator as a random Parallella user. Quite possibly way out of context. :)
* felix_ is back at the openfpga table
<nats`> I think I'll try to at 34c3
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<azonenberg> felix_: how's the turnout?
<balrog> well I'm here :P
<azonenberg> i meant of people we didn't know already